| /external/llvm/lib/Target/R600/ |
| H A D | R600MachineScheduler.cpp | 375 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass);
378 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass);
381 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass);
384 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);
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| H A D | SIFixSGPRCopies.cpp | 226 MRI.constrainRegClass(Reg, RC);
232 MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass);
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| /external/llvm/lib/CodeGen/ |
| H A D | OptimizePHIs.cpp | 170 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
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| H A D | UnreachableBlockElim.cpp | 197 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
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| H A D | MachineCSE.cpp | 152 if (!MRI->constrainRegClass(SrcReg, RC))
554 if (!MRI->constrainRegClass(NewReg, OldRC)) {
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| H A D | MachineRegisterInfo.cpp | 52 MachineRegisterInfo::constrainRegClass(unsigned Reg, function in class:MachineRegisterInfo
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| H A D | TailDuplication.cpp | 299 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
451 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg));
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| H A D | TwoAddressInstructionPass.cpp | 1322 MRI->constrainRegClass(DstReg, RC);
1437 MRI->constrainRegClass(RegA, RC);
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| H A D | PeepholeOptimizer.cpp | 388 MRI->constrainRegClass(DstReg, DstRC);
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| H A D | MachineBasicBlock.cpp | 369 if (!MRI.constrainRegClass(VirtReg, RC))
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| H A D | MachineLICM.cpp | 1359 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
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| H A D | RegisterCoalescer.cpp | 647 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 451 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
457 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
497 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
501 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
505 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
508 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
536 MRI.constrainRegClass(TrueReg, RC);
537 MRI.constrainRegClass(FalseReg, RC);
693 !MRI->constrainRegClass(Reg, OpRegCstraints))
1611 MF.getRegInfo().constrainRegClass(SrcRe
[all...] |
| H A D | AArch64ConditionalCompares.cpp | 604 MRI->constrainRegClass(HeadCond[2].getReg(),
651 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
654 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
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| H A D | AArch64RegisterInfo.cpp | 297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
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| H A D | AArch64FastISel.cpp | 585 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
674 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
798 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
1043 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
1172 MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass
1693 MRI.constrainRegClass(Reg32, &AArch64::GPR32RegClass);
1716 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
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| /external/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 155 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
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| H A D | A15SDOptimizer.cpp | 664 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
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| H A D | ARMBaseRegisterInfo.cpp | 596 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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| H A D | ARMLoadStoreOptimizer.cpp | 2051 MRI->constrainRegClass(EvenReg, TRC);
2052 MRI->constrainRegClass(OddReg, TRC);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1331 if (!MRI.constrainRegClass(Op, RegClass)) {
1433 MRI.constrainRegClass(Op0, RC);
1591 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
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| H A D | InstrEmitter.cpp | 332 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
444 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 514 /// constrainRegClass(ToReg, getRegClass(FromReg))
564 /// constrainRegClass - Constrain the register class of the specified virtual
571 const TargetRegisterClass *constrainRegClass(unsigned Reg,
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 957 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
982 MRI.constrainRegClass(BaseReg,
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 701 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
702 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
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