| /external/qemu/distrib/sdl-1.2.15/src/video/ataricommon/ |
| H A D | SDL_ataric2p.S | 50 moveml d2-d7/a2-a6,sp@-
80 movel d1,d7
81 lsrl #4,d7
82 eorl d0,d7
83 andl d4,d7
84 eorl d7,d0
85 lsll #4,d7
86 eorl d7,d1
88 movel d3,d7
89 lsrl #4,d7
[all...] |
| /external/llvm/test/MC/AArch64/ |
| H A D | neon-scalar-add-sub.s | 13 sub d1, d7, d8
15 // CHECK: sub d1, d7, d8 // encoding: [0xe1,0x84,0xe8,0x7e]
|
| /external/compiler-rt/lib/builtins/arm/ |
| H A D | adddf3vfp.S | 22 vmov d7, r2, r3 // move second param from r2/r3 pair into d7
23 vadd.f64 d6, d6, d7
|
| H A D | divdf3vfp.S | 22 vmov d7, r2, r3 // move second param from r2/r3 pair into d7
23 vdiv.f64 d5, d6, d7
|
| H A D | eqdf2vfp.S | 23 vmov d7, r2, r3 // load r2/r3 pair in double register
24 vcmp.f64 d6, d7
|
| H A D | extendsfdf2vfp.S | 23 vcvt.f64.f32 d7, s15 // convert single to double
24 vmov r0, r1, d7 // return result in r0/r1 pair
|
| H A D | fixdfsivfp.S | 22 vmov d7, r0, r1 // load double register from R0/R1
23 vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15
|
| H A D | fixunsdfsivfp.S | 23 vmov d7, r0, r1 // load double register from R0/R1
24 vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15
|
| H A D | floatsidfvfp.S | 23 vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7
24 vmov r0, r1, d7 // move d7 to result register pair r0/r1
|
| H A D | floatunssidfvfp.S | 23 vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7
24 vmov r0, r1, d7 // move d7 to result register pair r0/r1
|
| H A D | gedf2vfp.S | 23 vmov d7, r2, r3 // load r2/r3 pair in double register
24 vcmp.f64 d6, d7
|
| H A D | gtdf2vfp.S | 23 vmov d7, r2, r3 // load r2/r3 pair in double register
24 vcmp.f64 d6, d7
|
| H A D | ledf2vfp.S | 23 vmov d7, r2, r3 // load r2/r3 pair in double register
24 vcmp.f64 d6, d7
|
| H A D | ltdf2vfp.S | 23 vmov d7, r2, r3 // load r2/r3 pair in double register
24 vcmp.f64 d6, d7
|
| H A D | muldf3vfp.S | 22 vmov d7, r2, r3 // move second param from r2/r3 pair into d7
23 vmul.f64 d6, d6, d7
|
| H A D | nedf2vfp.S | 23 vmov d7, r2, r3 // load r2/r3 pair in double register
24 vcmp.f64 d6, d7
|
| H A D | subdf3vfp.S | 22 vmov d7, r2, r3 // move second param from r2/r3 pair into d7
23 vsub.f64 d6, d6, d7
|
| H A D | truncdfsf2vfp.S | 22 vmov d7, r0, r1 // load double from r0/r1 pair
23 vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
|
| H A D | unorddf2vfp.S | 23 vmov d7, r2, r3 // load r2/r3 pair in double register
24 vcmp.f64 d6, d7
|
| /external/llvm/test/MC/ARM/ |
| H A D | neon-bitwise-encoding.s | 124 vand d4, d7, d3
125 vand.8 d4, d7, d3
126 vand.16 d4, d7, d3
127 vand.32 d4, d7, d3
128 vand.64 d4, d7, d3
130 vand.i8 d4, d7, d3
131 vand.i16 d4, d7, d3
132 vand.i32 d4, d7, d3
133 vand.i64 d4, d7, d3
135 vand.s8 d4, d7, d
[all...] |
| /external/kernel-headers/original/uapi/linux/ |
| H A D | uuid.h | 35 #define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
40 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
42 #define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
47 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
|
| /external/libhevc/common/arm/ |
| H A D | ihevc_inter_pred_chroma_vert.s | 186 vdup.32 d7,d6[1]
187 vld1.32 {d7[1]},[r6],r2 @loads pu1_src_tmp
188 vmull.u8 q2,d7,d1 @vmull_u8(vreinterpret_u8_u32(src_tmp2), coeffabs_1)
189 vdup.32 d7,d7[1]
190 vld1.32 {d7[1]},[r6],r2
192 vmlal.u8 q2,d7,d2
193 vdup.32 d7,d7[1]
194 vld1.32 {d7[
[all...] |
| H A D | ihevc_inter_pred_chroma_vert_w16out.s | 186 vdup.32 d7,d6[1]
187 vld1.32 {d7[1]},[r6],r2 @loads pu1_src_tmp
188 vmull.u8 q2,d7,d1 @vmull_u8(vreinterpret_u8_u32(src_tmp2), coeffabs_1)
189 vdup.32 d7,d7[1]
190 vld1.32 {d7[1]},[r6],r2
192 vmlal.u8 q2,d7,d2
193 vdup.32 d7,d7[1]
194 vld1.32 {d7[
[all...] |
| H A D | ihevc_itrans_recon_32x32.s | 122 @d5[0]= 50 d7[0]=18
123 @d5[1]= 46 d7[1]=13
124 @d5[2]= 43 d7[2]=9
125 @d5[3]= 38 d7[3]=4
172 vld1.16 {d4,d5,d6,d7},[r14]!
254 vmlsl.s16 q15,d14,d7[1]
259 vmlsl.s16 q14,d15,d7[1]
268 vmlal.s16 q8,d13,d7[2]
269 vmlal.s16 q9,d12,d7[0]
287 vmlsl.s16 q13,d9,d7[
[all...] |
| H A D | ihevc_intra_pred_luma_planar.s | 152 vmov d7, d5 @mov #1 to d7 to used for inc for row+1 and dec for nt-1-row
200 vadd.s8 d5, d5, d7 @(1)
202 vsub.s8 d6, d6, d7 @(1)
215 vadd.s8 d5, d5, d7 @(2)
216 vsub.s8 d6, d6, d7 @(2)
232 vadd.s8 d5, d5, d7 @(3)
233 vsub.s8 d6, d6, d7 @(3)
249 vadd.s8 d5, d5, d7 @(4)
250 vsub.s8 d6, d6, d7
[all...] |