Searched refs:enablePostRAScheduler (Results 1 - 11 of 11) sorted by relevance

/external/llvm/lib/Target/
H A DTargetSubtargetInfo.cpp59 bool TargetSubtargetInfo::enablePostRAScheduler( function in class:TargetSubtargetInfo
/external/llvm/include/llvm/Target/
H A DTargetSubtargetInfo.h94 // enablePostRAScheduler - If the target can benefit from post-regalloc
99 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
/external/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.h228 /// enablePostRAScheduler - True at 'More' optimization.
229 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
H A DPPCSubtarget.cpp225 bool PPCSubtarget::enablePostRAScheduler( function in class:PPCSubtarget
/external/llvm/lib/Target/ARM/
H A DARMSubtarget.cpp437 bool ARMSubtarget::enablePostRAScheduler( function in class:ARMSubtarget
H A DARMSubtarget.h437 /// enablePostRAScheduler - True at 'More' optimization.
438 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
/external/llvm/lib/Target/Mips/
H A DMipsSubtarget.cpp180 MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, function in class:MipsSubtarget
H A DMipsSubtarget.h163 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
/external/llvm/lib/Target/X86/
H A DX86Subtarget.cpp363 X86Subtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, function in class:X86Subtarget
H A DX86Subtarget.h456 /// enablePostRAScheduler - run for Atom optimization.
457 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
/external/llvm/lib/CodeGen/
H A DPostRASchedulerList.cpp56 // TargetSubtargetInfo.enablePostRAScheduler(). This flag can be used to
271 if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,

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