/external/llvm/test/MC/Mips/ |
H A D | mips-fpu-instructions.s | 9 # CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46] 11 # CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46] 13 # CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46] 15 # CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46] 17 # CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46] 19 # CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46] 21 # CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46] 23 # CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46] 25 # CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46] 27 # CHECK: trunc.w.d $f12, [all...] |
/external/clang/test/CodeGen/ |
H A D | mangle-windows.c | 32 void f12(void) {} function 33 // CHECK: define void @f12(
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H A D | switch.c | 170 // CHECK-LABEL: define i32 @f12( 173 int f12(int x) { function
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/external/clang/test/Sema/ |
H A D | warn-unused-function.c | 43 static void f12(void) { } // expected-warning{{unused}} function 44 static void f12(void);
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H A D | attr-ownership.c | 16 void *f12(float i, int k, int f, int *j) __attribute__((ownership_returns(foo, 4))); // expected-error {{'ownership_returns' attribute only applies to integer arguments}}
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H A D | pragma-unused.c | 57 int f12(int x) { function
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/external/clang/test/CXX/except/except.spec/ |
H A D | p5-virtual.cpp | 41 virtual void f12() noexcept; 77 virtual void f12() throw();
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/external/llvm/test/MC/Mips/mips32r6/ |
H A D | invalid-mips5.s | 9 suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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H A D | invalid-mips32r2.s | 11 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 13 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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H A D | invalid-mips4.s | 9 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips4/ |
H A D | invalid-mips5.s | 9 suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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H A D | invalid-mips5-wrong-error.s | 11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/chromium_org/third_party/webrtc/modules/audio_processing/aec/ |
H A D | aec_rdft_mips.c | 272 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; local 381 "lwc1 %[f12], 4(%[p2_rdft]) \n\t" 398 "mul.s %[f0], %[f12], %[f0] \n\t" 403 "nmsub.s %[f7], %[f7], %[f12], %[f5] \n\t" 413 "mul.s %[f5], %[f12], %[f5] \n\t" 414 "mul.s %[f0], %[f12], %[f0] \n\t" 415 "mul.s %[f12], %[f13], %[f3] \n\t" 423 "sub.s %[f2], %[f12], %[f1] \n\t" 449 "lwc1 %[f12], 12(%[p2_rdft]) \n\t" 471 "nmsub.s %[f7], %[f7], %[f12], 521 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; local 929 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; local 1056 float f1, f2, f3 ,f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; local [all...] |
/external/chromium_org/v8/test/webkit/ |
H A D | toString-elision-trailing-comma.js | 73 function f12() { function 127 testToStringAndLength("f12", 2);
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/external/llvm/test/MC/SystemZ/ |
H A D | regs-good.s | 63 #CHECK: ler %f12, %f13 # encoding: [0x38,0xcd] 72 ler %f12,%f13 81 #CHECK: ldr %f12, %f13 # encoding: [0x28,0xcd] 90 ldr %f12,%f13 96 #CHECK: lxr %f12, %f13 # encoding: [0xb3,0x65,0x00,0xcd] 101 lxr %f12,%f13 131 #CHECK: .cfi_offset %f12, 224 165 .cfi_offset %f12,224
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/external/chromium_org/third_party/boringssl/src/crypto/perlasm/ |
H A D | sparcv9_modes.pl | 94 movxtod %o0, %f12 97 fxor %f12, %f0, %f0 ! ^= ivec 203 movxtod %o0, %f12 206 fxor %f12, %f0, %f0 ! ^= ivec 258 ldd [$ivec + 0], %f12 ! load ivec 262 faligndata %f12, %f14, %f12 267 ld [$ivec + 0], %f12 ! load ivec 317 fxor %f12, %f0, %f0 ! ^= ivec 319 movxtod %o0, %f12 [all...] |
/external/chromium_org/v8/test/cctest/ |
H A D | test-code-stubs-mips.cc | 65 // For softfp, move the input value into f12. 67 __ Move(f12, a0, a1); 71 __ sdc1(f12, MemOperand(sp)); 87 __ sdc1(f12, MemOperand(sp)); 91 __ ldc1(f12, MemOperand(source_reg)); 92 __ TryInlineTruncateDoubleToI(destination_reg, f12, &done);
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H A D | test-code-stubs-mips64.cc | 65 // For softfp, move the input value into f12. 67 __ Move(f12, a0, a1); 71 __ sdc1(f12, MemOperand(sp)); 87 __ sdc1(f12, MemOperand(sp)); 91 __ ldc1(f12, MemOperand(source_reg)); 92 __ TryInlineTruncateDoubleToI(destination_reg, f12, &done);
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/external/llvm/test/MC/Mips/mips3/ |
H A D | invalid-mips4.s | 11 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 20 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 27 movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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H A D | invalid-mips5-wrong-error.s | 11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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H A D | invalid-mips5.s | 12 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 21 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 28 movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 31 suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/DebugInfo/SystemZ/ |
H A D | eh_frame.s | 20 std %f12, 192(%r15) 28 .cfi_offset %f12, -192
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/external/llvm/test/MC/Mips/mips1/ |
H A D | invalid-mips5-wrong-error.s | 11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/Mips/mips2/ |
H A D | invalid-mips5-wrong-error.s | 11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 41 nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/Mips/mips32/ |
H A D | invalid-mips32r2.s | 14 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 19 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 22 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 32 suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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