| /external/compiler-rt/lib/builtins/ppc/ |
| H A D | restFP.S | 33 lfd f24,-64(r1)
|
| H A D | saveFP.S | 31 stfd f24,-64(r1)
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 8 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/ARM/ |
| H A D | symbol-variants.s | 82 .word f24(TLSDESC)
84 @ CHECK: 60 R_ARM_TLS_GOTDESC f24
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips32r2.s | 15 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | invalid-mips64r2.s | 18 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | valid.s | 10 add.s $f8,$f21,$f24
42 cvt.l.d $f24,$f15
48 cvt.w.s $f20,$f24
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 10 add.s $f8,$f21,$f24
39 cvt.l.d $f24,$f15
44 cvt.w.s $f20,$f24
84 mfhc1 $s8,$f24
128 nmsub.s $f1,$f24,$f19,$f4
|
| /external/clang/test/CodeGen/ |
| H A D | arm-arguments.c | 126 // APCS-GNU-LABEL: define i64 @f24()
132 // AAPCS: define arm_aapcscc void @f24({{.*}} noalias sret
138 _Complex int f24(void) {} function
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips64r2.s | 24 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | valid.s | 10 add.s $f8,$f21,$f24
40 cvt.l.d $f24,$f15
46 cvt.w.s $f20,$f24
|
| /external/openssl/crypto/ |
| H A D | alphacpuid.pl | 57 fclr $f24
|
| /external/chromium_org/v8/test/mjsunit/harmony/ |
| H A D | block-let-crankshaft.js | 34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26,
159 function f24() { function
|
| /external/valgrind/main/none/tests/mips32/ |
| H A D | MoveIns.c | 307 TESTINSNMOVE("mfc1 $t9, $f24", 28, f24, t9);
336 TESTINSNMOVEt("mtc1 $t9, $f24", 30, f24, t9);
365 TESTINSNMOVE1s("mov.s $f23, $f24", 28, f23, f24);
366 TESTINSNMOVE1s("mov.s $f24, $f25", 32, f24, f25);
393 TESTINSNMOVE1d("mov.d $f22, $f24", 40, f22, f24);
[all...] |
| /external/llvm/test/MC/ELF/ |
| H A D | cfi.s | 143 f24: label
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | valid.s | 10 add.s $f8,$f21,$f24
35 cvt.w.s $f20,$f24
|
| H A D | invalid-mips5-wrong-error.s | 45 puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | invalid-mips64r2.s | 28 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | valid.s | 10 add.s $f8,$f21,$f24
40 cvt.l.d $f24,$f15
46 cvt.w.s $f20,$f24
|
| /external/llvm/test/MC/PowerPC/ |
| H A D | ppc64-regs.s | 64 #CHECK: .cfi_offset f24, 500
181 .cfi_offset f24,500
|
| /external/oprofile/module/ia64/ |
| H A D | IA64entry.h | 47 .spillsp f24, SW(F24)+16+(off); .spillsp f25, SW(F25)+16+(off); \
|
| H A D | oprofile_stubs.S | 117 ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips32r2.s | 12 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
28 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
56 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 10 add.s $f8,$f21,$f24
42 cvt.l.d $f24,$f15
48 cvt.w.s $f20,$f24
143 mfhc1 $s8,$f24
186 nmsub.s $f1,$f24,$f19,$f4
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 10 add.s $f8,$f21,$f24
38 cvt.l.d $f24,$f15
44 cvt.w.s $f20,$f24
|