/external/compiler-rt/lib/builtins/ppc/ |
H A D | restFP.S | 34 lfd f25,-56(r1)
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H A D | saveFP.S | 32 stfd f25,-56(r1)
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/external/llvm/test/MC/Mips/mips32r6/ |
H A D | invalid-mips32r2.s | 9 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 13 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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H A D | invalid-mips32.s | 23 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips1/ |
H A D | invalid-mips5-wrong-error.s | 10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 30 cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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H A D | invalid-mips2.s | 8 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips2/ |
H A D | invalid-mips5-wrong-error.s | 10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 30 cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/Mips/mips3/ |
H A D | invalid-mips5-wrong-error.s | 10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 30 cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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H A D | invalid-mips4.s | 28 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips4/ |
H A D | invalid-mips5-wrong-error.s | 10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 30 cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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H A D | invalid-mips64r2.s | 20 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 31 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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H A D | valid.s | 6 abs.d $f7,$f25 # CHECK: encoding: 33 ceil.w.d $f11,$f25 137 movz.s $f25,$f7,$v1 158 round.l.s $f25,$f5
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/external/llvm/test/MC/Mips/mips64r6/ |
H A D | invalid-mips5-wrong-error.s | 9 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 37 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 42 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction 44 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
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/external/llvm/test/MC/ARM/ |
H A D | symbol-variants.s | 83 .word f25(tlsdesc) 85 @ CHECK: 64 R_ARM_TLS_GOTDESC f25
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/external/llvm/test/MC/Mips/mips64/ |
H A D | invalid-mips64r2.s | 17 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 21 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips32r2/ |
H A D | valid.s | 6 abs.d $f7,$f25 # CHECK: encoding: 31 ceil.w.d $f11,$f25 79 madd.s $f1,$f31,$f19,$f25 103 movz.s $f25,$f7,$v1 126 nmadd.s $f0,$f5,$f25,$f12
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/external/clang/test/CodeGen/ |
H A D | arm-arguments.c | 127 // APCS-GNU-LABEL: define i128 @f25() 133 // AAPCS: define arm_aapcscc void @f25({{.*}} noalias sret 139 _Complex long long f25(void) {} function
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/external/llvm/test/MC/Mips/mips32/ |
H A D | invalid-mips32r2.s | 16 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 22 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/openssl/crypto/ |
H A D | alphacpuid.pl | 58 fclr $f25
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/external/chromium_org/v8/test/mjsunit/harmony/ |
H A D | block-let-crankshaft.js | 34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26, 172 function f25() { function
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/external/llvm/test/MC/Mips/mips64r2/ |
H A D | valid.s | 6 abs.d $f7,$f25 # CHECK: encoding: 33 ceil.w.d $f11,$f25 138 madd.s $f1,$f31,$f19,$f25 164 movz.s $f25,$f7,$v1 185 nmadd.s $f0,$f5,$f25,$f12 198 round.l.s $f25,$f5
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/external/llvm/test/MC/ELF/ |
H A D | cfi.s | 149 f25: label
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/external/llvm/test/MC/Mips/mips5/ |
H A D | invalid-mips64r2.s | 24 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 35 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/PowerPC/ |
H A D | ppc64-regs.s | 65 #CHECK: .cfi_offset f25, 508 182 .cfi_offset f25,508
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/external/oprofile/module/ia64/ |
H A D | IA64entry.h | 47 .spillsp f24, SW(F24)+16+(off); .spillsp f25, SW(F25)+16+(off); \
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