Searched refs:f25 (Results 1 - 25 of 65) sorted by relevance

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/external/compiler-rt/lib/builtins/ppc/
H A DrestFP.S34 lfd f25,-56(r1)
H A DsaveFP.S32 stfd f25,-56(r1)
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips32r2.s9 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips32.s23 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips5-wrong-error.s10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
30 cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
H A Dinvalid-mips2.s8 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips5-wrong-error.s10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
30 cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5-wrong-error.s10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
30 cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
H A Dinvalid-mips4.s28 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips5-wrong-error.s10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
30 cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
H A Dinvalid-mips64r2.s20 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
31 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dvalid.s6 abs.d $f7,$f25 # CHECK: encoding:
33 ceil.w.d $f11,$f25
137 movz.s $f25,$f7,$v1
158 round.l.s $f25,$f5
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips5-wrong-error.s9 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
37 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
42 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
44 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/ARM/
H A Dsymbol-variants.s83 .word f25(tlsdesc)
85 @ CHECK: 64 R_ARM_TLS_GOTDESC f25
/external/llvm/test/MC/Mips/mips64/
H A Dinvalid-mips64r2.s17 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s6 abs.d $f7,$f25 # CHECK: encoding:
31 ceil.w.d $f11,$f25
79 madd.s $f1,$f31,$f19,$f25
103 movz.s $f25,$f7,$v1
126 nmadd.s $f0,$f5,$f25,$f12
/external/clang/test/CodeGen/
H A Darm-arguments.c127 // APCS-GNU-LABEL: define i128 @f25()
133 // AAPCS: define arm_aapcscc void @f25({{.*}} noalias sret
139 _Complex long long f25(void) {} function
/external/llvm/test/MC/Mips/mips32/
H A Dinvalid-mips32r2.s16 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/openssl/crypto/
H A Dalphacpuid.pl58 fclr $f25
/external/chromium_org/v8/test/mjsunit/harmony/
H A Dblock-let-crankshaft.js34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26,
172 function f25() { function
/external/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s6 abs.d $f7,$f25 # CHECK: encoding:
33 ceil.w.d $f11,$f25
138 madd.s $f1,$f31,$f19,$f25
164 movz.s $f25,$f7,$v1
185 nmadd.s $f0,$f5,$f25,$f12
198 round.l.s $f25,$f5
/external/llvm/test/MC/ELF/
H A Dcfi.s149 f25: label
/external/llvm/test/MC/Mips/mips5/
H A Dinvalid-mips64r2.s24 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
35 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/PowerPC/
H A Dppc64-regs.s65 #CHECK: .cfi_offset f25, 508
182 .cfi_offset f25,508
/external/oprofile/module/ia64/
H A DIA64entry.h47 .spillsp f24, SW(F24)+16+(off); .spillsp f25, SW(F25)+16+(off); \

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