| /external/compiler-rt/lib/builtins/ppc/ |
| H A D | restFP.S | 35 lfd f26,-48(r1)
|
| H A D | saveFP.S | 33 stfd f26,-48(r1)
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips5-wrong-error.s | 16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
27 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
46 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| H A D | valid.s | 31 cvt.d.w $f26,$f11
32 cvt.s.d $f26,$f8
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips5-wrong-error.s | 16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
27 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
46 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | invalid-mips5-wrong-error.s | 16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
27 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
46 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| H A D | valid.s | 37 cvt.d.w $f26,$f11
40 cvt.s.d $f26,$f8
89 floor.l.d $f26,$f7
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips5-wrong-error.s | 16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
27 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
46 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| H A D | valid.s | 39 cvt.d.w $f26,$f11
42 cvt.s.d $f26,$f8
91 floor.l.d $f26,$f7
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips5-wrong-error.s | 19 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
30 c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
45 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
46 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
48 sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/ARM/ |
| H A D | symbol-variants.s | 88 .word f26(GOT_PREL) + (. - .Lsym)
90 @ CHECK: 68 R_ARM_GOT_PREL f26
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips32r2.s | 8 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/clang/test/CodeGen/ |
| H A D | arm-arguments.c | 128 // APCS-GNU-LABEL: define i64 @f26()
134 // AAPCS: define arm_aapcscc void @f26({{.*}} noalias sret
140 _Complex float f26(void) {} function
|
| /external/openssl/crypto/ |
| H A D | alphacpuid.pl | 59 fclr $f26
|
| /external/chromium_org/v8/test/mjsunit/harmony/ |
| H A D | block-let-crankshaft.js | 34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26,
186 function f26() { function
|
| /external/llvm/test/MC/ELF/ |
| H A D | cfi.s | 155 f26: label
|
| /external/llvm/test/MC/PowerPC/ |
| H A D | ppc64-regs.s | 66 #CHECK: .cfi_offset f26, 516
183 .cfi_offset f26,516
|
| /external/oprofile/module/ia64/ |
| H A D | IA64entry.h | 48 .spillsp f26, SW(F26)+16+(off); .spillsp f27, SW(F27)+16+(off); \
|
| H A D | oprofile_stubs.S | 118 ldf.fill f26=[sp]; ldf.fill f27=[sp]; mov f28=f0
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 38 cvt.d.w $f26,$f11
41 cvt.s.d $f26,$f8
78 madd.d $f18,$f19,$f26,$f20
|
| /external/valgrind/main/none/tests/mips32/ |
| H A D | MoveIns.c | 309 TESTINSNMOVE("mfc1 $t2, $f26", 36, f26, t2);
338 TESTINSNMOVEt("mtc1 $t2, $f26", 38, f26, t2);
367 TESTINSNMOVE1s("mov.s $f25, $f26", 36, f25, f26);
395 TESTINSNMOVE1d("mov.d $f24, $f26", 56, f24, f26);
396 TESTINSNMOVE1d("mov.d $f24, $f26", 64, f24, f26);
[all...] |
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 39 cvt.d.w $f26,$f11
42 cvt.s.d $f26,$f8
91 floor.l.d $f26,$f7
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 41 cvt.d.w $f26,$f11
44 cvt.s.d $f26,$f8
96 floor.l.d $f26,$f7
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 15 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/chromium_org/third_party/mesa/src/src/mesa/sparc/ |
| H A D | sparc_matrix.h | 45 #define M10 %f26
|