| /external/llvm/test/MC/Sparc/ |
| H A D | sparc-vis.s | 3 ! CHECK: fzeros %f31 ! encoding: [0xbf,0xb0,0x0c,0x20]
4 fzeros %f31
|
| /external/openssl/crypto/ |
| H A D | ppccpuid.pl | 47 fmr f0,f31
48 fmr f1,f31
49 fmr f2,f31
51 fmr f3,f31
53 fmr f4,f31
55 fmr f5,f31
57 fmr f6,f31
59 fmr f7,f31
61 fmr f8,f31
63 fmr f9,f31
[all...] |
| /external/compiler-rt/lib/builtins/ppc/ |
| H A D | restFP.S | 17 // If the compiler wants to restore f27..f31, it does a "b restFP+52"
40 lfd f31,-8(r1)
|
| H A D | saveFP.S | 15 // If the compiler wants to save f27..f31, it does a "bl saveFP+52"
38 stfd f31,-8(r1)
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips32r2.s | 9 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips2-wrong-error.s | 14 sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| H A D | invalid-mips5-wrong-error.s | 22 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
34 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| H A D | invalid-mips3-wrong-error.s | 20 sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| H A D | invalid-mips4-wrong-error.s | 20 sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips5-wrong-error.s | 22 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
34 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | invalid-mips5-wrong-error.s | 22 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
34 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips5-wrong-error.s | 22 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
34 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| H A D | invalid-mips64r2.s | 20 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips5-wrong-error.s | 25 c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
36 movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
|
| /external/clang/test/CodeGen/ |
| H A D | arm-arguments.c | 160 void f31(struct s31 s) { } function
161 // AAPCS: @f31([1 x i32] %s.coerce)
165 // APCS-GNU: @f31([1 x i32] %s.coerce)
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 16 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/chromium_org/v8/test/mjsunit/harmony/ |
| H A D | block-let-crankshaft.js | 35 f27, f28, f29, f30, f31, f32, f33];
258 function f31() { function
|
| /external/llvm/test/MC/ELF/ |
| H A D | cfi.s | 185 f31: label
|
| /external/llvm/test/MC/PowerPC/ |
| H A D | ppc64-regs.s | 71 #CHECK: .cfi_offset f31, 556
188 .cfi_offset f31,556
|
| /external/oprofile/module/ia64/ |
| H A D | IA64entry.h | 50 .spillsp f30, SW(F30)+16+(off); .spillsp f31, SW(F31)+16+(off); \
|
| H A D | oprofile_stubs.S | 119 ldf.fill f29=[sp]; ldf.fill f30=[sp]; mov f31=f0
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | invalid-mips64r2.s | 17 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 79 madd.s $f1,$f31,$f19,$f25
105 msub.d $f10,$f1,$f31,$f18
145 sdc1 $f31,30574($13)
|
| /external/libunwind/tests/ |
| H A D | ia64-test-nat-asm.S | 385 .spillreg.p p6, r5, f31
386 (p6) setf.sig f31 = r5 // save r5 in f31 if it's a NaT
420 (p6) getf.sig r5 = f31
|
| /external/chromium_org/third_party/mesa/src/src/mesa/sparc/ |
| H A D | sparc_matrix.h | 50 #define M15 %f31
|