| /external/vixl/src/a64/ |
| H A D | simulator-a64.cc | 1439 int fbits = 64 - instr->FPScale(); local
1447 set_dreg(dst, FixedToDouble(xreg(src), fbits, round));
1450 set_dreg(dst, FixedToDouble(wreg(src), fbits, round));
1453 set_dreg(dst, UFixedToDouble(xreg(src), fbits, round));
1457 UFixedToDouble(static_cast<uint32_t>(wreg(src)), fbits, round));
1461 set_sreg(dst, FixedToFloat(xreg(src), fbits, round));
1464 set_sreg(dst, FixedToFloat(wreg(src), fbits, round));
1467 set_sreg(dst, UFixedToFloat(xreg(src), fbits, round));
1471 UFixedToFloat(static_cast<uint32_t>(wreg(src)), fbits, round));
1802 double Simulator::FixedToDouble(int64_t src, int fbits, FPRoundin argument
1812 UFixedToDouble(uint64_t src, int fbits, FPRounding round) argument
1828 FixedToFloat(int64_t src, int fbits, FPRounding round) argument
1838 UFixedToFloat(uint64_t src, int fbits, FPRounding round) argument
[all...] |
| H A D | simulator-a64.h | 530 double FixedToDouble(int64_t src, int fbits, FPRounding round_mode);
531 double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode);
532 float FixedToFloat(int64_t src, int fbits, FPRounding round_mode);
533 float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode);
|
| H A D | assembler-a64.cc | 1488 unsigned fbits) {
1489 if (fbits == 0) {
1492 Emit(SF(rn) | FPType(fd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
1500 unsigned fbits) {
1501 if (fbits == 0) {
1504 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
1486 scvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
1498 ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
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| H A D | macro-assembler-a64.h | 917 void Scvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0) {
920 scvtf(fd, rn, fbits);
1023 void Ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0) {
1026 ucvtf(fd, rn, fbits);
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| H A D | assembler-a64.h | 1368 void scvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0);
1371 void ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0);
|
| /external/chromium_org/v8/src/arm64/ |
| H A D | simulator-arm64.cc | 2302 int fbits = 64 - instr->FPScale(); local
2310 set_dreg(dst, FixedToDouble(xreg(src), fbits, round));
2313 set_dreg(dst, FixedToDouble(wreg(src), fbits, round));
2316 set_dreg(dst, UFixedToDouble(xreg(src), fbits, round));
2320 UFixedToDouble(reg<uint32_t>(src), fbits, round));
2324 set_sreg(dst, FixedToFloat(xreg(src), fbits, round));
2327 set_sreg(dst, FixedToFloat(wreg(src), fbits, round));
2330 set_sreg(dst, UFixedToFloat(xreg(src), fbits, round));
2334 UFixedToFloat(reg<uint32_t>(src), fbits, round));
2668 double Simulator::FixedToDouble(int64_t src, int fbits, FPRoundin argument
2678 UFixedToDouble(uint64_t src, int fbits, FPRounding round) argument
2694 FixedToFloat(int64_t src, int fbits, FPRounding round) argument
2704 UFixedToFloat(uint64_t src, int fbits, FPRounding round) argument
[all...] |
| H A D | simulator-arm64.h | 719 double FixedToDouble(int64_t src, int fbits, FPRounding round_mode);
720 double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode);
721 float FixedToFloat(int64_t src, int fbits, FPRounding round_mode);
722 float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode);
|
| H A D | macro-assembler-arm64-inl.h | 1070 unsigned fbits) {
1072 scvtf(fd, rn, fbits);
1174 unsigned fbits) {
1176 ucvtf(fd, rn, fbits);
1068 Scvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
1172 Ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
|
| H A D | assembler-arm64.cc | 2046 unsigned fbits) {
2047 if (fbits == 0) {
2050 Emit(SF(rn) | FPType(fd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2058 unsigned fbits) {
2059 if (fbits == 0) {
2062 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2044 scvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
2056 ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits) argument
|
| H A D | assembler-arm64.h | 1715 void scvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0);
1718 void ucvtf(const FPRegister& fd, const Register& rn, unsigned fbits = 0);
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| H A D | macro-assembler-arm64.h | 476 unsigned fbits = 0);
510 unsigned fbits = 0);
|
| /external/chromium_org/v8/test/cctest/ |
| H A D | test-assembler-arm64.cc | 7649 // value. All possible values of 'fbits' are tested. The expected value is
7699 // Test all possible values of fbits.
7700 for (int fbits = 1; fbits <= 32; fbits++) {
7701 __ Scvtf(d0, x10, fbits);
7702 __ Ucvtf(d1, x10, fbits);
7703 __ Scvtf(d2, w11, fbits);
7704 __ Ucvtf(d3, w11, fbits);
7705 __ Str(d0, MemOperand(x0, fbits * kDRegSiz
[all...] |
| /external/vixl/test/ |
| H A D | test-assembler-a64.cc | 6844 // value. All possible values of 'fbits' are tested. The expected value is
6894 // Test all possible values of fbits.
6895 for (int fbits = 1; fbits <= 32; fbits++) {
6896 __ Scvtf(d0, x10, fbits);
6897 __ Ucvtf(d1, x10, fbits);
6898 __ Scvtf(d2, w11, fbits);
6899 __ Ucvtf(d3, w11, fbits);
6900 __ Str(d0, MemOperand(x0, fbits * kDRegSizeInByte
[all...] |
| H A D | test-simulator-a64.cc | 168 unsigned fbits);
|