/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | SIRegisterInfo.cpp | 29 BitVector Reserved(getNumRegs());
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H A D | R600RegisterInfo.cpp | 29 BitVector Reserved(getNumRegs());
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/external/llvm/include/llvm/CodeGen/ |
H A D | LivePhysRegs.h | 56 LiveRegs.setUniverse(TRI->getNumRegs()); 64 LiveRegs.setUniverse(TRI->getNumRegs()); 76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); 86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | SIRegisterInfo.cpp | 29 BitVector Reserved(getNumRegs());
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H A D | R600RegisterInfo.cpp | 29 BitVector Reserved(getNumRegs());
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/external/llvm/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 56 CSRNum.resize(TRI->getNumRegs(), 0); 83 unsigned NumRegs = RC->getNumRegs(); 176 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
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H A D | CriticalAntiDepBreaker.cpp | 37 Classes(TRI->getNumRegs(), nullptr), 38 KillIndices(TRI->getNumRegs(), 0), 39 DefIndices(TRI->getNumRegs(), 0), 40 KeepRegs(TRI->getNumRegs(), false) {} 47 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { 108 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 256 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) 475 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { 529 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
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H A D | MachineRegisterInfo.cpp | 30 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs()); 34 new MachineOperand*[getTargetRegisterInfo()->getNumRegs()]; 36 sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs()); 62 if (NewRC->getNumRegs() < MinNumRegs) 167 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) 402 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
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H A D | StackMapLivenessAnalysis.cpp | 122 uint32_t *Mask = MF->allocateRegisterMask(TRI->getNumRegs());
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H A D | TargetRegisterInfo.cpp | 43 else if (TRI && Reg < TRI->getNumRegs()) 140 BitVector Allocatable(getNumRegs());
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H A D | RegisterScavenging.cpp | 78 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && 88 NumPhysRegs = TRI->getNumRegs(); 273 BitVector Mask(TRI->getNumRegs());
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H A D | ExecutionDepsFix.cpp | 157 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} 719 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); 739 AliasMap.resize(TRI->getNumRegs(), -1); 740 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
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H A D | InterferenceCache.cpp | 35 if (PhysRegEntriesCount == TRI->getNumRegs()) return; 37 PhysRegEntriesCount = TRI->getNumRegs();
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H A D | AggressiveAntiDepBreaker.cpp | 149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); 204 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 505 BitVector BV(TRI->getNumRegs(), false); 756 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
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H A D | CallingConvLower.cpp | 36 UsedRegs.resize((TRI.getNumRegs()+31)/32);
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/external/llvm/lib/Target/R600/ |
H A D | SIRegisterInfo.cpp | 27 BitVector Reserved(getNumRegs()); 37 return RC->getNumRegs();
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H A D | R600RegisterInfo.cpp | 28 BitVector Reserved(getNumRegs());
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 88 BitVector Reserved(getNumRegs());
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/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 58 /// getNumRegs - Return the number of registers in this class. 60 unsigned getNumRegs() const { return RegsSize; } function in class:llvm::MCRegisterClass 65 assert(i < getNumRegs() && "Register number out of range!"); 359 unsigned getNumRegs() const {
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/external/llvm/lib/MC/ |
H A D | MCRegisterInfo.cpp | 39 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
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/external/llvm/lib/Target/Mips/ |
H A D | MipsDelaySlotFiller.cpp | 289 : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false), 290 Uses(TRI.getNumRegs(), false) {} 313 BitVector CallerSavedRegs(TRI.getNumRegs(), true); 349 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
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/external/llvm/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 64 /// getNumRegs - Return the number of registers in this class. 66 unsigned getNumRegs() const { return MC->getNumRegs(); } function in class:llvm::TargetRegisterClass 195 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 431 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 37 BitVector Reserved(getNumRegs());
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64LoadStoreOptimizer.cpp | 414 ModifiedRegs.resize(TRI->getNumRegs()); 415 UsedRegs.resize(TRI->getNumRegs()); 665 ModifiedRegs.resize(TRI->getNumRegs()); 666 UsedRegs.resize(TRI->getNumRegs()); 718 ModifiedRegs.resize(TRI->getNumRegs()); 719 UsedRegs.resize(TRI->getNumRegs());
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.cpp | 34 UsedRegs.resize((TM.getRegisterInfo()->getNumRegs()+31)/32);
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