Searched refs:getOperand (Results 1 - 25 of 529) sorted by relevance

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/external/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp40 DestName = getRegName(MI->getOperand(0).getReg());
41 Src1Name = getRegName(MI->getOperand(1).getReg());
42 Src2Name = getRegName(MI->getOperand(2).getReg());
43 if(MI->getOperand(3).isImm())
44 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
49 Src2Name = getRegName(MI->getOperand(2).getReg());
50 Src1Name = getRegName(MI->getOperand(1).getReg());
51 DestName = getRegName(MI->getOperand(0).getReg());
57 Src2Name = getRegName(MI->getOperand(2).getReg());
58 Src1Name = getRegName(MI->getOperand(
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/external/llvm/lib/Target/R600/
H A DR600ClauseMergePass.cpp75 return MI->getOperand(
81 return MI->getOperand(
98 CFAlu->getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
123 if (LatrCFAlu->getOperand(Mode0Idx).getImm() &&
124 RootCFAlu->getOperand(Mode0Idx).getImm() &&
125 (LatrCFAlu->getOperand(KBank0Idx).getImm() !=
126 RootCFAlu->getOperand(KBank0Idx).getImm() ||
127 LatrCFAlu->getOperand(KBank0LineIdx).getImm() !=
128 RootCFAlu->getOperand(KBank0LineIdx).getImm())) {
139 if (LatrCFAlu->getOperand(Mode1Id
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H A DSILowerI1Copies.cpp88 I1Defs.push_back(MI.getOperand(0).getReg());
94 I1Defs.push_back(MI.getOperand(0).getReg());
100 I1Defs.push_back(MI.getOperand(0).getReg());
106 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()) ||
107 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(1).getReg()))
112 MRI.getRegClass(MI.getOperand(0).getReg());
114 MRI.getRegClass(MI.getOperand(1).getReg());
118 I1Defs.push_back(MI.getOperand(0).getReg());
120 .addOperand(MI.getOperand(0))
123 .addOperand(MI.getOperand(
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H A DSIFixSGPRCopies.cpp120 if (!MI.getOperand(i).isReg() ||
121 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
124 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
150 I->getOperand(0).getReg(),
151 I->getOperand(0).getSubReg()));
173 return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(),
174 Def->getOperand(1).getSubReg());
181 unsigned DstReg = Copy.getOperand(0).getReg();
182 unsigned SrcReg = Copy.getOperand(1).getReg();
183 unsigned SrcSubReg = Copy.getOperand(
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/external/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
35 .addImm(MI->getOperand(1).getImm());
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
40 .addImm(MI->getOperand(2).getImm());
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
49 .addImm(MI->getOperand(1).getImm());
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
54 .addImm(MI->getOperand(
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H A DSystemZElimCompare.cpp111 MI->getOperand(0).isReg() &&
112 MI->getOperand(0).isDef() &&
113 MI->getOperand(0).getReg() == Reg &&
114 MI->getOperand(0).getSubReg() == SubReg)
130 if (MI->getOperand(1).getReg() == Reg &&
131 MI->getOperand(1).getSubReg() == SubReg)
142 const MachineOperand &MO = MI->getOperand(I);
176 if (MI->getOperand(2).getImm() != -1)
184 Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
185 Branch->getOperand(
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/external/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp100 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
101 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
130 OutOps.push_back(Op.getOperand(0));
164 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
165 N->getOperand(2) };
170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
171 N->getOperand(2) };
176 SDValue Ops[] = { N->getOperand(
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/external/llvm/lib/IR/
H A DIntrinsicInst.cpp37 return CE->getOperand(0);
58 return MD->getOperand(0);
68 return cast<MDNode>(getArgOperand(0))->getOperand(0);
72 return cast<MDNode>(getArgOperand(0))->getOperand(0);
/external/llvm/lib/Target/Hexagon/
H A DHexagonSplitTFRCondSets.cpp98 int DestReg = MI->getOperand(0).getReg();
99 int SrcReg1 = MI->getOperand(2).getReg();
100 int SrcReg2 = MI->getOperand(3).getReg();
116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
128 int DestReg = MI->getOperand(0).getReg();
129 int SrcReg1 = MI->getOperand(2).getReg();
136 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
141 addReg(MI->getOperand(1).getReg()).
142 addImm(MI->getOperand(
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H A DHexagonNewValueJump.cpp149 if (II->getOperand(i).isReg() &&
150 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
153 unsigned Reg = II->getOperand(i).getReg();
228 int64_t v = MI->getOperand(2).getImm();
238 cmpReg1 = MI->getOperand(1).getReg();
241 cmpOp2 = MI->getOperand(2).getReg();
426 predReg = MI->getOperand(0).getReg();
431 // if(!jmpInstr->getOperand(0).isKill()) break;
455 jmpTarget = MI->getOperand(
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/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp343 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
382 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
415 SDValue Op0 = N->getOperand(0);
416 SDValue Op1 = N->getOperand(1);
436 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
437 Op0.getOperand(0).getOpcode() == ISD::SRL) {
438 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
439 Op1.getOperand(0).getOpcode() != ISD::SRL) {
446 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
447 Op1.getOperand(
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600ISelLowering.cpp66 .addOperand(MI->getOperand(0))
67 .addOperand(MI->getOperand(1))
77 .addOperand(MI->getOperand(0))
78 .addOperand(MI->getOperand(1))
89 .addOperand(MI->getOperand(0))
90 .addOperand(MI->getOperand(1))
99 int64_t RegIndex = MI->getOperand(1).getImm();
102 .addOperand(MI->getOperand(0))
109 unsigned maskedRegister = MI->getOperand(0).getReg();
135 .addOperand(MI->getOperand(
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H A DSIISelLowering.cpp83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI->getOperand(1))
98 .addOperand(MI->getOperand(0))
99 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(1))
103 .addOperand(MI->getOperand(1))
113 .addOperand(MI->getOperand(0))
114 .addOperand(MI->getOperand(
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/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ISelLowering.cpp66 .addOperand(MI->getOperand(0))
67 .addOperand(MI->getOperand(1))
77 .addOperand(MI->getOperand(0))
78 .addOperand(MI->getOperand(1))
89 .addOperand(MI->getOperand(0))
90 .addOperand(MI->getOperand(1))
99 int64_t RegIndex = MI->getOperand(1).getImm();
102 .addOperand(MI->getOperand(0))
109 unsigned maskedRegister = MI->getOperand(0).getReg();
135 .addOperand(MI->getOperand(
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H A DSIISelLowering.cpp83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI->getOperand(1))
98 .addOperand(MI->getOperand(0))
99 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(1))
103 .addOperand(MI->getOperand(1))
113 .addOperand(MI->getOperand(0))
114 .addOperand(MI->getOperand(
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/external/llvm/unittests/IR/
H A DMDBuilderTest.cpp39 Value *Op = MD1->getOperand(0);
53 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(0)));
54 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(1)));
55 ConstantInt *C0 = cast<ConstantInt>(R1->getOperand(0));
56 ConstantInt *C1 = cast<ConstantInt>(R1->getOperand(1));
67 EXPECT_EQ(R0->getOperand(0), R0);
68 EXPECT_EQ(R1->getOperand(0), R1);
69 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == nullptr);
70 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == nullptr);
78 EXPECT_TRUE(isa<MDString>(R0->getOperand(
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/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp86 switch (MI->getOperand(0).getImm()) {
112 const MCOperand &Dst = MI->getOperand(0);
113 const MCOperand &MO1 = MI->getOperand(1);
114 const MCOperand &MO2 = MI->getOperand(2);
115 const MCOperand &MO3 = MI->getOperand(3);
135 const MCOperand &Dst = MI->getOperand(0);
136 const MCOperand &MO1 = MI->getOperand(1);
137 const MCOperand &MO2 = MI->getOperand(2);
164 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
178 if (MI->getOperand(
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/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp88 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
91 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
96 Base = Addr.getOperand(0);
102 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
103 Base = Addr.getOperand(1);
104 Offset = Addr.getOperand(0).getOperand(0);
107 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
108 Base = Addr.getOperand(0);
109 Offset = Addr.getOperand(
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/external/llvm/lib/Target/SystemZ/InstPrinter/
H A DSystemZInstPrinter.cpp56 int64_t Value = MI->getOperand(OpNum).getImm();
63 int64_t Value = MI->getOperand(OpNum).getImm();
70 int64_t Value = MI->getOperand(OpNum).getImm();
77 int64_t Value = MI->getOperand(OpNum).getImm();
84 int64_t Value = MI->getOperand(OpNum).getImm();
91 int64_t Value = MI->getOperand(OpNum).getImm();
98 int64_t Value = MI->getOperand(OpNum).getImm();
105 int64_t Value = MI->getOperand(OpNum).getImm();
112 uint64_t Value = MI->getOperand(OpNum).getImm();
119 const MCOperand &MO = MI->getOperand(OpNu
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/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp391 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
396 SDValue MultHi = ADDENode->getOperand(0);
397 SDValue MultLo = ADDCNode->getOperand(0);
428 ADDCNode->getOperand(1),
429 ADDENode->getOperand(1));
435 MultNode->getOperand(0),// Factor 0
436 MultNode->getOperand(1),// Factor 1
463 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
468 SDValue MultHi = SUBENode->getOperand(1);
469 SDValue MultLo = SUBCNode->getOperand(
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/external/llvm/lib/CodeGen/
H A DAntiDepBreaker.h64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
65 MI->getOperand(0).setReg(NewReg);
/external/llvm/lib/Target/ARM/
H A DARMOptimizeBarriersPass.cpp68 if (MI.getOperand(0).getImm() == DMBType) {
73 DMBType = MI.getOperand(0).getImm();
78 DMBType = MI.getOperand(0).getImm();
H A DARMFeatures.h79 return Instr->getOperand(2).getReg() != ARM::PC;
84 return Instr->getOperand(0).getReg() != ARM::PC;
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(2).getReg() != ARM::PC;
90 return Instr->getOperand(0).getReg() != ARM::PC &&
91 Instr->getOperand(1).getReg() != ARM::PC;
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp44 isa<ConstantInt>(I->getOperand(2)))
50 (CheapToScalarize(BO->getOperand(0), isConstant) ||
51 CheapToScalarize(BO->getOperand(1), isConstant)))
55 (CheapToScalarize(CI->getOperand(0), isConstant) ||
56 CheapToScalarize(CI->getOperand(1), isConstant)))
77 if (!isa<ConstantInt>(III->getOperand(2)))
79 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue();
84 return III->getOperand(1);
88 return FindScalarElement(III->getOperand(0), EltNo);
92 unsigned LHSWidth = SVI->getOperand(
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/external/llvm/lib/Target/PowerPC/InstPrinter/
H A DPPCInstPrinter.cpp43 unsigned char SH = MI->getOperand(2).getImm();
44 unsigned char MB = MI->getOperand(3).getImm();
45 unsigned char ME = MI->getOperand(4).getImm();
66 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
76 unsigned char SH = MI->getOperand(2).getImm();
77 unsigned char ME = MI->getOperand(3).getImm();
109 unsigned Code = MI->getOperand(OpNo).getImm();
205 unsigned int Value = MI->getOperand(OpNo).getImm();
212 int Value = MI->getOperand(OpN
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