| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetMachine.cpp | 56 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
61 if (getOptLevel() != CodeGenOpt::None &&
91 if (getOptLevel() != CodeGenOpt::None)
93 if (getOptLevel() != CodeGenOpt::None)
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetMachine.cpp | 116 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
121 addPass(createHexagonISelDag(TM, getOptLevel()));
132 if (getOptLevel() != CodeGenOpt::None)
140 if (getOptLevel() != CodeGenOpt::None)
150 if (getOptLevel() != CodeGenOpt::None)
159 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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| H A D | HexagonFrameLowering.cpp | 153 if (hasFP(MF) || MF.getTarget().getOptLevel() == CodeGenOpt::None) {
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| H A D | HexagonCopyToCombine.cpp | 425 MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
|
| H A D | HexagonISelDAGToDAG.cpp | 1629 if (TM.getOptLevel() == CodeGenOpt::Aggressive)
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.cpp | 155 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
165 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
167 if (TM->getOptLevel() != CodeGenOpt::None)
169 if (TM->getOptLevel() != CodeGenOpt::None)
176 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
181 getOptLevel() != CodeGenOpt::None)
199 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar)
206 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
208 if (TM->getOptLevel() != CodeGenOpt::None &&
219 if (TM->getOptLevel() !
[all...] |
| /external/llvm/include/llvm/MC/ |
| H A D | MCCodeGenInfo.h | 44 CodeGenOpt::Level getOptLevel() const { return OptLevel; } function in class:llvm::MCCodeGenInfo
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86TargetMachine.cpp | 135 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
138 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
162 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
172 if (getOptLevel() != CodeGenOpt::None) {
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 168 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
175 if (TM->getOptLevel() != CodeGenOpt::None)
182 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
192 if (getOptLevel() != CodeGenOpt::None)
194 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
198 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
206 if (getOptLevel() != CodeGenOpt::None) {
218 if (getOptLevel() != CodeGenOpt::None) {
|
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430TargetMachine.cpp | 59 addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetMachine.cpp | 103 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
119 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
137 if (getOptLevel() != CodeGenOpt::None)
144 if (getOptLevel() != CodeGenOpt::None)
|
| /external/llvm/lib/CodeGen/ |
| H A D | Passes.cpp | 388 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
400 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
434 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
503 if (getOptLevel() != CodeGenOpt::None) {
531 if (getOptLevel() != CodeGenOpt::None)
543 if (getOptLevel() != CodeGenOpt::None) {
558 if (getOptLevel() != CodeGenOpt::None)
613 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
|
| H A D | LLVMTargetMachine.cpp | 123 (TM->getOptLevel() == CodeGenOpt::None &&
|
| H A D | PostRASchedulerList.cpp | 271 if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,
|
| H A D | TwoAddressInstructionPass.cpp | 1512 OptLevel = TM.getOptLevel();
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| H A D | RegAllocGreedy.cpp | 2328 TM.getSubtargetImpl()->enableRALocalReassignment(TM.getOptLevel());
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreTargetMachine.cpp | 60 addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 142 if (getOptLevel() == CodeGenOpt::Aggressive)
164 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
|
| /external/llvm/lib/Target/ |
| H A D | TargetMachine.cpp | 138 /// getOptLevel - Returns the optimization level: None, Less,
140 CodeGenOpt::Level TargetMachine::getOptLevel() const { function in class:TargetMachine
143 return CodeGenInfo->getOptLevel();
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | Passes.h | 139 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } function in class:llvm::TargetPassConfig
|
| /external/llvm/include/llvm/Target/ |
| H A D | TargetMachine.h | 177 /// getOptLevel - Returns the optimization level: None, Less,
179 CodeGenOpt::Level getOptLevel() const;
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsTargetMachine.cpp | 143 if (getOptLevel() == CodeGenOpt::None) {
|
| H A D | MipsDelaySlotFiller.cpp | 505 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDILPeepholeOptimizer.cpp | 166 optLevel = TM.getOptLevel();
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDILPeepholeOptimizer.cpp | 166 optLevel = TM.getOptLevel();
|