/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 40 DestName = getRegName(MI->getOperand(0).getReg()); 41 Src1Name = getRegName(MI->getOperand(1).getReg()); 42 Src2Name = getRegName(MI->getOperand(2).getReg()); 49 Src2Name = getRegName(MI->getOperand(2).getReg()); 50 Src1Name = getRegName(MI->getOperand(1).getReg()); 51 DestName = getRegName(MI->getOperand(0).getReg()); 57 Src2Name = getRegName(MI->getOperand(2).getReg()); 58 Src1Name = getRegName(MI->getOperand(1).getReg()); 59 DestName = getRegName(MI->getOperand(0).getReg()); 65 Src1Name = getRegName(MI->getOperand(2).getReg()); [all...] |
/external/dexmaker/src/dx/java/com/android/dx/dex/code/form/ |
H A D | Form23x.java | 71 unsignedFitsInByte(regs.get(0).getReg()) && 72 unsignedFitsInByte(regs.get(1).getReg()) && 73 unsignedFitsInByte(regs.get(2).getReg()); 82 bits.set(0, unsignedFitsInByte(regs.get(0).getReg())); 83 bits.set(1, unsignedFitsInByte(regs.get(1).getReg())); 84 bits.set(2, unsignedFitsInByte(regs.get(2).getReg())); 93 opcodeUnit(insn, regs.get(0).getReg()), 94 codeUnit(regs.get(1).getReg(), regs.get(2).getReg()));
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H A D | Form33x.java | 75 unsignedFitsInByte(regs.get(0).getReg()) && 76 unsignedFitsInByte(regs.get(1).getReg()) && 77 unsignedFitsInShort(regs.get(2).getReg()); 86 bits.set(0, unsignedFitsInByte(regs.get(0).getReg())); 87 bits.set(1, unsignedFitsInByte(regs.get(1).getReg())); 88 bits.set(2, unsignedFitsInShort(regs.get(2).getReg())); 98 codeUnit(regs.get(0).getReg(), regs.get(1).getReg()), 99 (short) regs.get(2).getReg());
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H A D | Form22t.java | 70 unsignedFitsInNibble(regs.get(0).getReg()) && 71 unsignedFitsInNibble(regs.get(1).getReg()))) { 85 bits.set(0, unsignedFitsInNibble(regs.get(0).getReg())); 86 bits.set(1, unsignedFitsInNibble(regs.get(1).getReg())); 107 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
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H A D | Form22x.java | 70 unsignedFitsInByte(regs.get(0).getReg()) && 71 unsignedFitsInShort(regs.get(1).getReg()); 80 bits.set(0, unsignedFitsInByte(regs.get(0).getReg())); 81 bits.set(1, unsignedFitsInShort(regs.get(1).getReg())); 90 opcodeUnit(insn, regs.get(0).getReg()), 91 (short) regs.get(1).getReg());
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H A D | Form32x.java | 69 unsignedFitsInShort(regs.get(0).getReg()) && 70 unsignedFitsInShort(regs.get(1).getReg()); 79 bits.set(0, unsignedFitsInShort(regs.get(0).getReg())); 80 bits.set(1, unsignedFitsInShort(regs.get(1).getReg())); 91 (short) regs.get(0).getReg(), 92 (short) regs.get(1).getReg());
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H A D | Form12x.java | 97 if (rs1.getReg() != regs.get(0).getReg()) { 107 return unsignedFitsInNibble(rs1.getReg()) && 108 unsignedFitsInNibble(rs2.getReg()); 117 bits.set(0, unsignedFitsInNibble(regs.get(0).getReg())); 118 bits.set(1, unsignedFitsInNibble(regs.get(1).getReg())); 135 makeByte(regs.get(sz - 2).getReg(), 136 regs.get(sz - 1).getReg())));
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H A D | Form21c.java | 92 if (reg.getReg() != regs.get(1).getReg()) { 102 if (!unsignedFitsInByte(reg.getReg())) { 125 boolean compat = unsignedFitsInByte(regs.get(0).getReg()); 130 if (regs.get(0).getReg() == regs.get(1).getReg()) { 146 opcodeUnit(insn, regs.get(0).getReg()),
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H A D | Form31c.java | 92 if (reg.getReg() != regs.get(1).getReg()) { 102 if (!unsignedFitsInByte(reg.getReg())) { 120 boolean compat = unsignedFitsInByte(regs.get(0).getReg()); 125 if (regs.get(0).getReg() == regs.get(1).getReg()) { 140 write(out, opcodeUnit(insn, regs.get(0).getReg()), cpi);
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H A D | Form41c.java | 95 if (reg.getReg() != regs.get(1).getReg()) { 105 if (!unsignedFitsInShort(reg.getReg())) { 122 boolean compat = unsignedFitsInByte(regs.get(0).getReg()); 127 if (regs.get(0).getReg() == regs.get(1).getReg()) { 142 write(out, opcodeUnit(insn), cpi, (short) regs.get(0).getReg());
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H A D | Form22b.java | 74 unsignedFitsInByte(regs.get(0).getReg()) && 75 unsignedFitsInByte(regs.get(1).getReg()))) { 97 bits.set(0, unsignedFitsInByte(regs.get(0).getReg())); 98 bits.set(1, unsignedFitsInByte(regs.get(1).getReg())); 110 opcodeUnit(insn, regs.get(0).getReg()), 111 codeUnit(regs.get(1).getReg(), value & 0xff));
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H A D | Form22c.java | 76 unsignedFitsInNibble(regs.get(0).getReg()) && 77 unsignedFitsInNibble(regs.get(1).getReg()))) { 99 bits.set(0, unsignedFitsInNibble(regs.get(0).getReg())); 100 bits.set(1, unsignedFitsInNibble(regs.get(1).getReg())); 112 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
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H A D | Form22s.java | 74 unsignedFitsInNibble(regs.get(0).getReg()) && 75 unsignedFitsInNibble(regs.get(1).getReg()))) { 97 bits.set(0, unsignedFitsInNibble(regs.get(0).getReg())); 98 bits.set(1, unsignedFitsInNibble(regs.get(1).getReg())); 111 makeByte(regs.get(0).getReg(), regs.get(1).getReg())),
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H A D | Form32s.java | 78 unsignedFitsInByte(regs.get(0).getReg()) && 79 unsignedFitsInByte(regs.get(1).getReg()))) { 101 bits.set(0, unsignedFitsInByte(regs.get(0).getReg())); 102 bits.set(1, unsignedFitsInByte(regs.get(1).getReg())); 115 codeUnit(regs.get(0).getReg(), regs.get(1).getReg()),
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H A D | Form52c.java | 80 unsignedFitsInShort(regs.get(0).getReg()) && 81 unsignedFitsInShort(regs.get(1).getReg()))) { 98 bits.set(0, unsignedFitsInShort(regs.get(0).getReg())); 99 bits.set(1, unsignedFitsInShort(regs.get(1).getReg())); 112 (short) regs.get(0).getReg(), 113 (short) regs.get(1).getReg());
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H A D | Form35c.java | 113 bits.set(i, unsignedFitsInNibble(reg.getReg() + 126 int r0 = (sz > 0) ? regs.get(0).getReg() : 0; 127 int r1 = (sz > 1) ? regs.get(1).getReg() : 0; 128 int r2 = (sz > 2) ? regs.get(2).getReg() : 0; 129 int r3 = (sz > 3) ? regs.get(3).getReg() : 0; 130 int r4 = (sz > 4) ? regs.get(4).getReg() : 0; 168 if (!unsignedFitsInNibble(one.getReg() + one.getCategory() - 1)) { 201 RegisterSpec.make(one.getReg() + 1, Type.VOID));
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H A D | Form11x.java | 69 unsignedFitsInByte(regs.get(0).getReg()); 78 bits.set(0, unsignedFitsInByte(regs.get(0).getReg())); 86 write(out, opcodeUnit(insn, regs.get(0).getReg()));
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFeatures.h | 79 return Instr->getOperand(2).getReg() != ARM::PC; 84 return Instr->getOperand(0).getReg() != ARM::PC; 86 return Instr->getOperand(0).getReg() != ARM::PC && 87 Instr->getOperand(2).getReg() != ARM::PC; 90 return Instr->getOperand(0).getReg() != ARM::PC && 91 Instr->getOperand(1).getReg() != ARM::PC;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitTFRCondSets.cpp | 98 int DestReg = MI->getOperand(0).getReg(); 99 int SrcReg1 = MI->getOperand(2).getReg(); 100 int SrcReg2 = MI->getOperand(3).getReg(); 116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 128 int DestReg = MI->getOperand(0).getReg(); 129 int SrcReg1 = MI->getOperand(2).getReg(); 136 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 141 addReg(MI->getOperand(1).getReg()). 146 addReg(MI->getOperand(1).getReg()) [all...] |
/external/dexmaker/src/dx/java/com/android/dx/ssa/ |
H A D | DeadCodeRemover.java | 108 useList[source.getReg()].remove(insnS); 112 source.getReg()))) { 117 worklist.set(source.getReg()); 154 useList[source.getReg()].remove(insn); 160 for (SsaInsn use : useList[result.getReg()]) { 204 || !isCircularNoSideEffect(result.getReg(), set)) { 252 noSideEffectRegs.set(insn.getResult().getReg()); 260 noSideEffectRegs.set(phi.getResult().getReg()); 268 noSideEffectRegs.set(result.getReg());
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZAsmPrinter.cpp | 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) 48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) 61 .addReg(MI->getOperand(0).getReg()) 62 .addReg(MI->getOperand(1).getReg()) 63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) 86 .addReg(MI->getOperand(0).getReg()); [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 122 printRegName(O, Dst.getReg()); 124 printRegName(O, MO1.getReg()); 127 printRegName(O, MO2.getReg()); 144 printRegName(O, Dst.getReg()); 146 printRegName(O, MO1.getReg()); 164 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 178 if (MI->getOperand(2).getReg() == ARM::SP && 183 printRegName(O, MI->getOperand(1).getReg()); 193 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { 207 if (MI->getOperand(2).getReg() [all...] |
/external/llvm/lib/Target/R600/ |
H A D | SILowerI1Copies.cpp | 88 I1Defs.push_back(MI.getOperand(0).getReg()); 94 I1Defs.push_back(MI.getOperand(0).getReg()); 100 I1Defs.push_back(MI.getOperand(0).getReg()); 106 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()) || 107 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(1).getReg())) 112 MRI.getRegClass(MI.getOperand(0).getReg()); 114 MRI.getRegClass(MI.getOperand(1).getReg()); 118 I1Defs.push_back(MI.getOperand(0).getReg());
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H A D | SIFixSGPRCopies.cpp | 121 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg())) 124 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 150 I->getOperand(0).getReg(), 173 return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(), 181 unsigned DstReg = Copy.getOperand(0).getReg(); 182 unsigned SrcReg = Copy.getOperand(1).getReg(); 223 unsigned Reg = MI.getOperand(i).getReg(); 228 unsigned Reg = MI.getOperand(0).getReg(); 241 unsigned Reg = MI.getOperand(i).getReg(); 263 DstRC = MRI.getRegClass(MI.getOperand(0).getReg()); [all...] |
/external/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 51 O << getRegisterName(Op.getReg()); 74 if (!Base.getReg()) 85 if (Base.getReg()) 86 O << '(' << getRegisterName(Base.getReg()) << ')';
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