Searched refs:getSchedulingPreference (Results 1 - 7 of 7) sorted by relevance

/external/llvm/lib/Target/ARM/
H A DARMISelLowering.h369 Sched::Preference getSchedulingPreference(SDNode *N) const override;
H A DARMISelLowering.cpp1104 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { function in class:ARMTargetLowering
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h384 Sched::Preference getSchedulingPreference(SDNode *N) const override;
H A DPPCISelLowering.cpp8993 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { function in class:PPCTargetLowering
8995 return TargetLowering::getSchedulingPreference(N);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp291 TLI->getSchedulingPreference() == Sched::Source)
293 if (TLI->getSchedulingPreference() == Sched::RegPressure)
295 if (TLI->getSchedulingPreference() == Sched::Hybrid)
297 if (TLI->getSchedulingPreference() == Sched::VLIW)
299 assert(TLI->getSchedulingPreference() == Sched::ILP &&
H A DScheduleDAGSDNodes.cpp86 SU->SchedulingPref = TLI.getSchedulingPreference(N);
/external/llvm/include/llvm/Target/
H A DTargetLowering.h301 Sched::Preference getSchedulingPreference() const { function in class:llvm::TargetLoweringBase
308 virtual Sched::Preference getSchedulingPreference(SDNode *) const { function in class:llvm::TargetLoweringBase

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