| /external/vixl/src/a64/ |
| H A D | instructions-a64.cc | 58 // indicate a failure case. Specifically, where the constraints on imm_s are
63 int64_t imm_s = ImmSetBits(); local
66 // An integer is constructed from the n, imm_s and imm_r bits according to
84 if (imm_s == 0x3F) {
87 uint64_t bits = (UINT64_C(1) << (imm_s + 1)) - 1;
90 if ((imm_s >> 1) == 0x1F) {
94 if ((imm_s & width) == 0) {
96 if ((imm_s & mask) == mask) {
99 uint64_t bits = (UINT64_C(1) << ((imm_s & mask) + 1)) - 1;
|
| H A D | assembler-a64.cc | 1663 unsigned n, imm_s, imm_r; local
1664 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) {
1666 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
1683 unsigned imm_s,
1689 ImmSetBits(imm_s, reg_size) | ImmRotate(imm_r, reg_size) | dest_reg |
1914 // imm_s and imm_r are updated with immediates encoded in the format required
1917 // to by n, imm_s and imm_r are undefined.
1921 unsigned* imm_s,
1923 VIXL_ASSERT((n != NULL) && (imm_s != NULL) && (imm_r != NULL));
1926 // Logical immediates are encoded using parameters n, imm_s an
1680 LogicalImmediate(const Register& rd, const Register& rn, unsigned n, unsigned imm_s, unsigned imm_r, LogicalOp op) argument
1918 IsImmLogical(uint64_t value, unsigned width, unsigned* n, unsigned* imm_s, unsigned* imm_r) argument
[all...] |
| H A D | macro-assembler-a64.cc | 176 unsigned n, imm_s, imm_r; local
177 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) {
179 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
292 unsigned n, imm_s, imm_r; local
301 } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) {
304 LogicalImmediate(rd, AppropriateZeroRegFor(rd), n, imm_s, imm_r, ORR);
|
| H A D | assembler-a64.h | 1715 unsigned imm_s,
1721 unsigned* imm_s,
|
| /external/chromium_org/v8/src/arm64/ |
| H A D | instructions-arm64.cc | 92 // indicate a failure case. Specifically, where the constraints on imm_s are not
97 int64_t imm_s = ImmSetBits(); local
100 // An integer is constructed from the n, imm_s and imm_r bits according to
118 if (imm_s == 0x3F) {
121 uint64_t bits = (1UL << (imm_s + 1)) - 1;
124 if ((imm_s >> 1) == 0x1F) {
128 if ((imm_s & width) == 0) {
130 if ((imm_s & mask) == mask) {
133 uint64_t bits = (1UL << ((imm_s & mask) + 1)) - 1;
|
| H A D | assembler-arm64.cc | 2277 unsigned n, imm_s, imm_r; local
2278 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) {
2280 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
2297 unsigned imm_s,
2303 ImmSetBits(imm_s, reg_size) | ImmRotate(imm_r, reg_size) | dest_reg |
2527 // imm_s and imm_r are updated with immediates encoded in the format required
2530 // to by n, imm_s and imm_r are undefined.
2534 unsigned* imm_s,
2536 DCHECK((n != NULL) && (imm_s != NULL) && (imm_r != NULL));
2541 // Logical immediates are encoded using parameters n, imm_s an
2294 LogicalImmediate(const Register& rd, const Register& rn, unsigned n, unsigned imm_s, unsigned imm_r, LogicalOp op) argument
2531 IsImmLogical(uint64_t value, unsigned width, unsigned* n, unsigned* imm_s, unsigned* imm_r) argument
[all...] |
| H A D | macro-assembler-arm64.cc | 122 unsigned n, imm_s, imm_r; local
123 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) {
125 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
417 unsigned n, imm_s, imm_r; local
429 } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) {
431 LogicalImmediate(dst, AppropriateZeroRegFor(dst), n, imm_s, imm_r, ORR);
|
| H A D | assembler-arm64.h | 1838 unsigned* imm_s,
1951 unsigned imm_s,
|
| /external/valgrind/main/VEX/priv/ |
| H A D | host_arm64_isel.c | 1226 /*OUT*/UInt* imm_s, /*OUT*/UInt* imm_r,
1233 // pointed to by n, imm_s and imm_r are updated with immediates
1236 // returns false, and the values pointed to by n, imm_s and imm_r
1238 vassert(n != NULL && imm_s != NULL && imm_r != NULL);
1241 // Logical immediates are encoded using parameters n, imm_s and imm_r using
1287 *imm_s = 0x3C;
1293 *imm_s = ((imm_s_fixed | (set_bits - 1)) & imm_s_mask);
1334 UInt n = 0, imm_s = 0, imm_r = 0; local
1335 Bool ok = isImmLogical(&n, &imm_s, &imm_r, imm64, 64);
1337 vassert(n < 2 && imm_s < 6
1225 isImmLogical( UInt* n, UInt* imm_s, UInt* imm_r, ULong value, UInt width ) argument
[all...] |