| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.h | 70 static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) { argument
72 return isPPC64 ? 16 : 8;
74 return isPPC64 ? 16 : 4;
85 static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) { argument
92 return isPPC64 ? -8U : -4U;
95 return isPPC64 ? -8U : -4U;
100 static unsigned getBasePointerSaveOffset(bool isPPC64, bool isDarwinABI) { argument
102 return isPPC64 ? -16U : -8U;
105 return isPPC64 ? -16U : -8U;
110 static unsigned getLinkageSize(bool isPPC64, boo argument
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| H A D | PPCFrameLowering.cpp | 49 if (Subtarget.isPPC64()) {
189 if (Subtarget.isPPC64()) {
385 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
402 unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
511 bool isPPC64 = Subtarget.isPPC64(); local
548 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
549 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30;
550 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
551 unsigned LRReg = isPPC64
838 bool isPPC64 = Subtarget.isPPC64(); local
1068 bool isPPC64 = Subtarget.isPPC64(); local
1426 restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) argument
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| H A D | PPCAsmPrinter.cpp | 308 bool isPPC64 = Subtarget.isPPC64(); local
480 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
499 TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ);
531 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
547 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
563 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
583 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
599 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
615 assert(Subtarget.isPPC64()
757 bool isPPC64 = TD->getPointerSizeInBits() == 64; local
889 bool isPPC64 = TM.getDataLayout()->getPointerSizeInBits() == 64; local
1025 bool isPPC64 = TM.getDataLayout()->getPointerSizeInBits() == 64; local
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| H A D | PPCSubtarget.cpp | 51 if (!ST.isPPC64() || T.getOS() == Triple::Lv2)
56 if (ST.isPPC64() || ST.isSVR4ABI())
62 if (ST.isPPC64())
233 if (isPPC64())
|
| H A D | PPCRegisterInfo.cpp | 60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
61 ST.isPPC64() ? 0 : 1,
62 ST.isPPC64() ? 0 : 1),
90 if (Subtarget.isPPC64())
95 if (Subtarget.isPPC64())
103 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
110 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
121 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
128 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
181 if (Subtarget.isPPC64()) {
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| H A D | PPCInstrInfo.cpp | 341 bool isPPC64 = Subtarget.isPPC64(); local
398 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
409 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
467 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
481 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
547 bool isPPC64 = Subtarget.isPPC64(); local
555 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
556 (isPPC64
1044 bool isPPC64 = Subtarget.isPPC64(); local
1111 bool isPPC64 = Subtarget.isPPC64(); local
1133 bool isPPC64 = Subtarget.isPPC64(); local
1171 bool isPPC64 = Subtarget.isPPC64(); local
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| H A D | PPCISelLowering.cpp | 74 bool isPPC64 = Subtarget.isPPC64(); local
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
106 isPPC64 ? MVT::i64 : MVT::i32);
109 isPPC64 ? MVT::i64 : MVT::i32);
300 if (isPPC64) {
319 if (Subtarget.isSVR4ABI() && !isPPC64)
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
629 if (isPPC64) {
1916 bool isPPC64 = (PtrVT == MVT::i64); local
2720 bool isPPC64 = PtrVT == MVT::i64; local
3174 EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, bool isPPC64, bool isDarwinABI, SDLoc dl) argument
3215 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) argument
3279 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, SDLoc dl) argument
3304 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, bool isDarwinABI, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) argument
3337 bool isPPC64 = Subtarget.isPPC64(); local
4369 bool isPPC64 = PtrVT == MVT::i64; local
4818 bool isPPC64 = Subtarget.isPPC64(); local
4844 bool isPPC64 = Subtarget.isPPC64(); local
4868 bool isPPC64 = Subtarget.isPPC64(); local
8794 bool isPPC64 = Subtarget.isPPC64(); local
8821 bool isPPC64 = PtrVT == MVT::i64; local
8849 bool isPPC64 = Subtarget.isPPC64(); local
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| H A D | PPCSubtarget.h | 166 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
168 bool isPPC64() const { return IsPPC64; } function in class:llvm::PPCSubtarget
|
| H A D | PPCTargetTransformInfo.cpp | 258 if (ST->isPPC64() &&
294 if (ST->isPPC64())
|
| H A D | PPCJITInfo.cpp | 29 : Subtarget(STI), is64Bit(STI.isPPC64()) {
|
| H A D | PPCISelDAGToDAG.cpp | 749 bool isPPC64 = (PtrVT == MVT::i64); local
766 if (isPPC64) break;
790 if (isPPC64) break;
799 if (isPPC64) break;
1269 bool isPPC64 = (PtrVT == MVT::i64); local
1277 if (!isPPC64)
1388 bool IsPPC64 = PPCSubTarget->isPPC64();
1448 assert (PPCSubTarget->isPPC64() && "Only supported for 64-bit ABI");
2043 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
|
| H A D | PPCFastISel.cpp | 2270 if (Subtarget->isPPC64() && Subtarget->isSVR4ABI())
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCMCTargetDesc.cpp | 52 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || local
54 unsigned Flavour = isPPC64 ? 0 : 1;
55 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
71 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || local
76 MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
78 MAI = new PPCLinuxMCAsmInfo(isPPC64, TheTriple);
81 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
|
| H A D | PPCMCCodeEmitter.cpp | 275 bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le; local
276 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 227 bool isPPC64() const { return IsPPC64; } function in class:__anon26071::PPCAsmParser
358 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
359 bool isPPC64() const { return IsPPC64; } function in struct:__anon26071::PPCOperand
468 if (isPPC64())
475 if (isPPC64())
963 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
967 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
976 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1235 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1250 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
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