Searched refs:lane (Results 1 - 9 of 9) sorted by relevance

/external/tcpdump/
H A DAndroid.mk17 print-l2tp.c print-lane.c print-ldp.c print-lldp.c print-llc.c \
/external/tcpdump/win32/prj/
H A DGNUmakefile91 ../../print-lane.o \
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir_emit_nv50.cpp120 void emitQUADOP(const Instruction *, uint8_t lane, uint8_t quOp);
779 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) argument
781 code[0] = 0xc0000000 | (lane << 16);
/external/mesa3d/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir_emit_nv50.cpp120 void emitQUADOP(const Instruction *, uint8_t lane, uint8_t quOp);
779 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) argument
781 code[0] = 0xc0000000 | (lane << 16);
/external/valgrind/main/VEX/priv/
H A Dguest_arm64_toIR.c960 /* Find the offset of the laneNo'th lane of type laneTy in the given
961 Qreg. Since the host is little-endian, the least significant lane
967 /* Since the host is little-endian, the least significant lane
987 /* Put to the least significant lane of a Qreg. */
1002 /* Get from the least significant lane of a Qreg. */
1087 /* Put to a specified lane of a Qreg. */
1104 /* Get from a specified lane of a Qreg. */
5199 and Iop_CatOdd* operators to 'src' so as to clone each lane into
5201 zero out all but the least significant lane. */
5401 /* A vector containing 15 in each 8-bit lane */
7323 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8); local
7330 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8); local
7337 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16); local
7344 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16); local
7351 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32); local
7358 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32); local
7365 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I64); local
[all...]
H A Dguest_x86_toIR.c513 least significant lane (rightmost in the register). */
7056 /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */
7091 /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */
7156 /* Lowest 32-bit lane only unary SSE operation, G = op(E). */
7199 /* Lowest 64-bit lane only unary SSE operation, G = op(E). */
7779 values (aa,bb), computes, for each lane:
7818 value aa, computes, for each lane
8522 assign( argR, getXMMRegLane32F( eregOfRM(modrm), 0/*lowest lane*/ ) );
8533 assign( argL, getXMMRegLane32F( gregOfRM(modrm), 0/*lowest lane*/ ) );
8865 put it into the specified lane o
8870 Int lane; local
10960 Int lane; local
10981 putXMMRegLane16( gregOfRM(modrm), lane & 7, mkexpr(t4) ); local
[all...]
H A Dguest_amd64_toIR.c1409 least significant lane (rightmost in the register). */
8769 /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */
8805 /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */
8872 /* Lowest 32-bit lane only unary SSE operation, G = op(E). */
8916 /* Lowest 64-bit lane only unary SSE operation, G = op(E). */
9586 values (aa,bb), computes, for each lane:
9626 value aa, computes, for each lane
9960 0/*lowest lane*/ ) );
9976 0/*lowest lane*/ ) );
10003 0/*lowest lane*/ ) );
13768 Int lane; local
13809 Int lane; local
[all...]
/external/libpcap/
H A Dscanner.l288 lane return LANE;
/external/valgrind/main/none/tests/arm/
H A Dneon64.stdout.exp1992 ---- VLD1 (single element to one lane) ----
2027 ---- VLD2 (single 2-element structure to one lane) ----
2065 ---- VLD3 (single 3-element structure to one lane) ----
2103 ---- VLD4 (single 4-element structure to one lane) ----
2155 ---- VST1 (single element from one lane) ----
2180 ---- VST2 (single 2-element structure from one lane) ----
2208 ---- VST3 (single 3-element structure from one lane) ----
2236 ---- VST4 (single 4-element structure from one lane) ----
2278 ---- VLD1 (single element to one lane) ----
2313 ---- VLD2 (single 2-element structure to one lane)
[all...]

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