Searched refs:lwl (Results 1 - 25 of 35) sorted by relevance

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/external/llvm/test/MC/Mips/
H A Dmicromips-loadstore-unaligned.s12 # CHECK-EL: lwl $4, 16($5) # encoding: [0x85,0x60,0x10,0x00]
19 # CHECK-EB: lwl $4, 16($5) # encoding: [0x60,0x85,0x00,0x10]
23 lwl $4, 16($5)
H A Dnacl-mask.s52 lwl $4, 0($9)
91 # CHECK-NEXT: lwl $4, 0($9)
/external/chromium_org/v8/src/mips/
H A Dcodegen-mips.cc143 __ lwl(t8, MemOperand(a1));
301 __ lwl(v1,
307 __ lwl(v1, MemOperand(a1));
361 __ lwl(t0,
363 __ lwl(t1,
365 __ lwl(t2,
367 __ lwl(t3,
369 __ lwl(t4,
371 __ lwl(t5,
373 __ lwl(t
[all...]
H A Ddisasm-mips.cc1176 Format(instr, "lwl 'rt, 'imm16s('rs)");
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips1-wrong-error.s10 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips1-wrong-error.s10 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
H A Dinvalid-mips3-wrong-error.s16 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/openssl/crypto/sha/asm/
H A Dsha1-mips.S39 lwl $8,3($5)
52 lwl $9,1*4+3($5)
76 lwl $10,2*4+3($5)
100 lwl $11,3*4+3($5)
124 lwl $12,4*4+3($5)
148 lwl $13,5*4+3($5)
172 lwl $14,6*4+3($5)
196 lwl $15,7*4+3($5)
220 lwl $16,8*4+3($5)
244 lwl
[all...]
H A Dsha256-mips.S49 lwl $8,3($5)
51 lwl $9,7($5)
103 lwl $10,11($5)
155 lwl $11,15($5)
207 lwl $12,19($5)
259 lwl $13,23($5)
311 lwl $14,27($5)
363 lwl $15,31($5)
415 lwl $16,35($5)
467 lwl
[all...]
H A Dsha1-mips.pl13 # to deploy lwl/lwr pair to load unaligned input. One could have
109 lwl @X[$j],$j*4+$MSB($inp)
287 lwl @X[0],$MSB($inp)
/external/openssl/crypto/aes/asm/
H A Daes-mips.S41 lwl $12,2($1) # Te1[s1>>16]
42 lwl $13,2($2) # Te1[s2>>16]
43 lwl $14,2($24) # Te1[s3>>16]
44 lwl $15,2($25) # Te1[s0>>16]
62 lwl $16,1($1) # Te2[s2>>8]
63 lwl $17,1($2) # Te2[s3>>8]
64 lwl $18,1($24) # Te2[s0>>8]
65 lwl $19,1($25) # Te2[s1>>8]
83 lwl $20,0($1) # Te3[s3]
84 lwl
[all...]
H A Daes-mips.pl18 # additional rotations. Rotations are implemented with lwl/lwr pairs,
142 lwl $t0,3($i0) # Te1[s1>>16]
143 lwl $t1,3($i1) # Te1[s2>>16]
144 lwl $t2,3($i2) # Te1[s3>>16]
145 lwl $t3,3($i3) # Te1[s0>>16]
163 lwl $t4,2($i0) # Te2[s2>>8]
164 lwl $t5,2($i1) # Te2[s3>>8]
165 lwl $t6,2($i2) # Te2[s0>>8]
166 lwl $t7,2($i3) # Te2[s1>>8]
184 lwl
[all...]
/external/chromium_org/v8/src/mips64/
H A Dcodegen-mips64.cc301 __ lwl(v1,
352 __ lwl(a4,
354 __ lwl(a5,
356 __ lwl(a6,
358 __ lwl(a7,
360 __ lwl(t0,
362 __ lwl(t1,
364 __ lwl(t2,
366 __ lwl(t3,
385 __ lwl(a
[all...]
H A Ddisasm-mips64.cc1310 Format(instr, "lwl 'rt, 'imm16s('rs)");
/external/pixman/pixman/
H A Dpixman-mips-memcpy-asm.S38 # define LWHI lwl /* high part is left in big-endian */
45 # define LWLO lwl /* low part is left in big-endian */
/external/llvm/test/MC/Mips/mips1/
H A Dvalid.s51 lwl $s4,-4231($15)
/external/llvm/test/MC/Mips/mips2/
H A Dvalid.s59 lwl $s4,-4231($15)
/external/llvm/test/MC/Mips/mips32/
H A Dvalid.s64 lwl $s4,-4231($15)
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s73 lwl $s4,-4231($15)
/external/chromium_org/v8/test/cctest/
H A Dtest-assembler-mips.cc854 __ lwl(t0, MemOperand(a0, OFFSET_OF(T, mem_init)) );
858 __ lwl(t1, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) );
862 __ lwl(t2, MemOperand(a0, OFFSET_OF(T, mem_init) + 2) );
866 __ lwl(t3, MemOperand(a0, OFFSET_OF(T, mem_init) + 3) );
H A Dtest-assembler-mips64.cc888 __ lwl(a4, MemOperand(a0, OFFSET_OF(T, mem_init)));
892 __ lwl(a5, MemOperand(a0, OFFSET_OF(T, mem_init) + 1));
896 __ lwl(a6, MemOperand(a0, OFFSET_OF(T, mem_init) + 2));
900 __ lwl(a7, MemOperand(a0, OFFSET_OF(T, mem_init) + 3));
/external/linux-tools-perf/perf-3.12.0/arch/mips/lib/
H A Dmemcpy.S140 #define LOADL lwl
/external/qemu/target-mips/
H A Dhelper.h13 DEF_HELPER_4(lwl, tl, env, tl, tl, int)
/external/llvm/test/MC/Mips/mips3/
H A Dvalid.s109 lwl $s4,-4231($15)
/external/llvm/test/MC/Mips/mips4/
H A Dvalid.s112 lwl $s4,-4231($15)

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