Searched refs:memop (Results 1 - 5 of 5) sorted by relevance
| /external/chromium_org/v8/src/arm/ |
| H A D | disasm-arm.cc | 522 if (format[1] == 'e') { // 'memop: load/store instructions.
523 DCHECK(STRING_STARTS_WITH(format, "memop"));
746 Format(instr, "'memop'cond's 'rd, ['rn], -'rm");
748 Format(instr, "'memop'cond's 'rd, ['rn], #-'off8");
754 Format(instr, "'memop'cond's 'rd, ['rn], +'rm");
756 Format(instr, "'memop'cond's 'rd, ['rn], #+'off8");
762 Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w");
764 Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w");
770 Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w");
772 Format(instr, "'memop'con
[all...] |
| /external/qemu/tcg/ |
| H A D | tcg.c | 859 void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) argument
861 memop = tcg_canonicalize_memop(memop, 0, 0);
867 *tcg_ctx.gen_opparam_ptr++ = memop;
873 assert((memop & MO_BSWAP) == MO_TE || (memop & MO_SIZE) == MO_8);
874 assert(old_ld_opc[memop & MO_SSIZE] != 0);
877 *tcg_ctx.gen_opc_ptr++ = old_ld_opc[memop & MO_SSIZE];
884 *tcg_ctx.gen_opc_ptr++ = old_ld_opc[memop & MO_SSIZE];
894 void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) argument
930 tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) argument
936 tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); local
965 tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) argument
971 tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); local
[all...] |
| /external/vixl/src/a64/ |
| H A D | assembler-a64.cc | 1054 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | local
1069 Emit(addrmodeop | memop);
1841 Instr memop = op | Rt(rt) | RnSP(addr.base()); local
1848 Emit(LoadStoreUnsignedOffsetFixed | memop |
1852 Emit(LoadStoreUnscaledOffsetFixed | memop | ImmLS(offset));
1871 Emit(LoadStoreRegisterOffsetFixed | memop | Rm(addr.regoffset()) |
1876 Emit(LoadStorePreIndexFixed | memop | ImmLS(offset));
1879 Emit(LoadStorePostIndexFixed | memop | ImmLS(offset));
|
| /external/qemu/tcg/i386/ |
| H A D | tcg-target.c | 1343 TCGMemOp memop)
1345 const TCGMemOp bswap = memop & MO_BSWAP;
1347 switch (memop & MO_SSIZE) {
1483 TCGMemOp memop)
1485 const TCGMemOp bswap = memop & MO_BSWAP;
1493 switch (memop & MO_SIZE) {
1341 tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, intptr_t ofs, int seg, TCGMemOp memop) argument
1481 tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, intptr_t ofs, int seg, TCGMemOp memop) argument
|
| /external/chromium_org/v8/src/arm64/ |
| H A D | assembler-arm64.cc | 1606 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | local
1624 Emit(addrmodeop | memop);
2457 Instr memop = op | Rt(rt) | RnSP(addr.base()); local
2464 Emit(LoadStoreUnsignedOffsetFixed | memop |
2468 Emit(LoadStoreUnscaledOffsetFixed | memop | ImmLS(offset));
2487 Emit(LoadStoreRegisterOffsetFixed | memop | Rm(addr.regoffset()) |
2494 Emit(LoadStorePreIndexFixed | memop | ImmLS(offset));
2497 Emit(LoadStorePostIndexFixed | memop | ImmLS(offset));
|
Completed in 130 milliseconds