Searched refs:mfhi (Results 1 - 25 of 34) sorted by relevance

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/external/openssl/crypto/bn/asm/
H A Dbn-mips.S41 mfhi $12
54 mfhi $14
68 mfhi $8
81 mfhi $10
102 mfhi $12
117 mfhi $12
131 mfhi $12
170 mfhi $12
181 mfhi $14
189 mfhi
[all...]
H A Dmips-mont.S55 mfhi $11
61 mfhi $17
65 mfhi $25
71 mfhi $19
91 mfhi $17
101 mfhi $19
138 mfhi $11
147 mfhi $17
151 mfhi $25
158 mfhi
[all...]
H A Dmips.pl158 mfhi $t0
171 mfhi $t2
185 mfhi $ta0
198 mfhi $ta2
219 mfhi $t0
234 mfhi $t0
248 mfhi $t0
311 mfhi $t0
322 mfhi $t2
330 mfhi
[all...]
H A Dmips3.s93 mfhi t0
106 mfhi t2
120 mfhi ta0
133 mfhi ta2
157 mfhi t0
172 mfhi t0
186 mfhi t0
216 mfhi t0
227 mfhi t2
235 mfhi ta
[all...]
H A Dmips3-mont.pl98 mfhi $hi0
104 mfhi $ahi
108 mfhi $hi1
114 mfhi $nhi
134 mfhi $ahi
144 mfhi $nhi
181 mfhi $hi0
190 mfhi $ahi
194 mfhi $hi1
201 mfhi
[all...]
H A Dmips-mont.pl183 mfhi $hi0
189 mfhi $ahi
193 mfhi $hi1
199 mfhi $nhi
219 mfhi $ahi
229 mfhi $nhi
266 mfhi $hi0
275 mfhi $ahi
279 mfhi $hi1
286 mfhi
[all...]
/external/llvm/test/MC/Mips/
H A Dmicromips-16-bit-instructions.s12 # CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
19 # CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
24 mfhi $9
H A Dmips-dsp-instructions.s35 # CHECK: mfhi $14, $ac1 # encoding: [0x00,0x20,0x70,0x10]
46 # CHECK: mfhi $14 # encoding: [0x00,0x00,0x70,0x10]
83 mfhi $14, $ac1
94 mfhi $14
H A Dmips-fpu-instructions.s147 # CHECK: mfhi $5 # encoding: [0x10,0x28,0x00,0x00]
182 mfhi $a1
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips1.s13 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips2.s9 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips1.s16 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips2.s12 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips3.s14 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips64.s23 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/chromium_org/v8/test/cctest/
H A Dtest-disasm-mips.cc407 COMPARE(mfhi(a0),
408 "00002010 mfhi a0");
409 COMPARE(mfhi(s2),
410 "00009010 mfhi s2");
411 COMPARE(mfhi(t4),
412 "00006010 mfhi t4");
413 COMPARE(mfhi(v1),
414 "00001810 mfhi v1");
H A Dtest-disasm-mips64.cc560 COMPARE(mfhi(a0),
561 "00002010 mfhi a0");
562 COMPARE(mfhi(s2),
563 "00009010 mfhi s2");
564 COMPARE(mfhi(t0),
565 "00006010 mfhi t0");
566 COMPARE(mfhi(v1),
567 "00001810 mfhi v1");
/external/llvm/test/MC/Mips/mips1/
H A Dvalid.s54 mfhi $s3
55 mfhi $sp
/external/llvm/test/MC/Mips/mips2/
H A Dvalid.s62 mfhi $s3
63 mfhi $sp
/external/llvm/test/MC/Mips/mips32/
H A Dvalid.s72 mfhi $s3
73 mfhi $sp
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s85 mfhi $s3
86 mfhi $sp
/external/llvm/test/MC/Mips/mips3/
H A Dvalid.s113 mfhi $s3
114 mfhi $sp
/external/llvm/test/MC/Mips/mips4/
H A Dvalid.s117 mfhi $s3
118 mfhi $sp
/external/llvm/test/MC/Mips/mips5/
H A Dvalid.s118 mfhi $s3
119 mfhi $sp
/external/llvm/test/MC/Mips/mips64/
H A Dvalid.s128 mfhi $s3
129 mfhi $sp

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