Searched refs:movt (Results 1 - 25 of 62) sorted by relevance

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/external/llvm/test/MC/ARM/
H A Dtarget-expressions.s19 movt r0, :upper16:function
22 movt r1, #:upper16:function
25 movt r2, :upper16:deadbeat
28 movt r3, #:upper16:deadbeat
31 movt r4, :upper16:0xD1510D6E
34 movt r5, #:upper16:0xD1510D6E
37 movt r0, :upper16:external
40 movt r1, #:upper16:external
43 movt r2, #:upper16:(16 + 16)
46 movt r
[all...]
H A Dthumb2be-movt-encoding.s4 movt r9, :upper16:(_bar) label
5 @ CHECK-LE: movt r9, :upper16:_bar @ encoding: [0xc0'A',0xf2'A',0b0000AAAA,0x09]
7 @ CHECK-BE: movt r9, :upper16:_bar @ encoding: [0xf2,0b1100AAAA,0x09'A',A]
H A Dhilo-16bit-relocations.s6 movt r0, :upper16:(L_foo$non_lazy_ptr - (L1 + 8))
10 @ CHECK: movt r0, :upper16:(L_foo$non_lazy_ptr-(L1+8))
H A D2010-11-30-reloc-movt.s14 .file "/home/espindola/llvm/llvm/test/CodeGen/ARM/2010-11-30-reloc-movt.ll"
23 movt r0, :upper16:a
H A Dbig-endian-thumb2-fixup.s17 movt r0, :upper16:GOT-(movt_label)
H A Darm_fixups.s14 movt r9, :upper16:(_foo)
24 @ CHECK: movt r9, :upper16:_foo @ encoding: [A,0x90'A',0b0100AAAA,0xe3]
26 @ CHECK-BE: movt r9, :upper16:_foo @ encoding: [0xe3,0b0100AAAA,0x90'A',A]
H A Delf-movt.s12 movt r0, :upper16:GOT-(.LPC0_2+8)
15 @ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8))
H A Dbig-endian-arm-fixup.s81 movt r0, :upper16:GOT-(movt_label)
H A Dcoff-relocations.s37 movt r0, :upper16:target
42 @ CHECK-ENCODING-NEXT: movt r0, #0
/external/llvm/test/MC/MachO/ARM/
H A Dthumb2-movt-fixup.s4 movt r3, :upper16:(_wilma-(LPC0_0+4))
H A Dthumb2-movw-fixup.s11 movt r2, :upper16:L1
13 movt r12, :upper16:L2
H A Dstatic-movt-relocs.s6 movt r0, :upper16:(bar + 16)
/external/valgrind/main/none/tests/mips32/
H A DMoveIns.stdout.exp227 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
228 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
229 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
230 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
231 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
232 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
233 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
234 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
235 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
236 movt
[all...]
/external/llvm/test/MC/Mips/
H A Dmicromips-movcond-instructions.s14 # CHECK-EL: movt $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x09]
21 # CHECK-EB: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b]
25 movt $9, $6, $fcc0
/external/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips4.s21 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
23 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
H A Dinvalid-mips5.s22 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
24 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/valgrind/main/coregrind/m_dispatch/
H A Ddispatch-arm-linux.S129 4 = movt r12, hi16(disp_cp_chain_me_to_slowEP)
144 4 = movt r12, hi16(disp_cp_chain_me_to_fastEP)
157 movt r1, #:upper16:vgPlain_stats__n_xindirs_32
168 movt r4, #:upper16:VG_(tt_fast) // r4 = &VG_(tt_fast)
182 movt r1, #:upper16:vgPlain_stats__n_xindir_misses_32
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips32.s18 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/ARM/Windows/
H A Dmov32t-range.s19 movt r0, :upper16:.Lerange
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips32.s31 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
33 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
35 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
H A Dinvalid-mips32r2.s38 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
39 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
40 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
H A Dinvalid-mips4.s60 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
61 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
62 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
64 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
H A Dinvalid-mips5.s59 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
60 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
61 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
62 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips64.s32 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/armv7/
H A DomxSP_FFTInv_CToC_FC32_Sfs_s.S153 movt round, #0x3f80 @// round = 1.0

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