Searched refs:nregs (Results 1 - 25 of 37) sorted by relevance

12

/external/libunwind/src/ia64/
H A DGrbs.c128 unw_word_t nregs, bsp = c->bsp, curr = c->rbs_curr, n; local
149 nregs = rse_num_regs (bsp, c->rbs_area[curr].end);
151 if (regs_to_skip < nregs)
170 regs_to_skip -= nregs;
199 rbs_cover_and_flush (struct cursor *c, unw_word_t nregs, argument
209 c->bsp = rse_skip_regs (bsp, nregs);
215 if (likely (n >= nregs))
232 nregs -= n; /* account for registers already on the rbs */
234 assert (rse_skip_regs (c->bsp, -nregs) == rse_skip_regs (rbs->end, 0));
239 nregs
[all...]
/external/elfutils/0.153/libdwfl/
H A Ddwfl_module_register_names.c74 int nregs = ebl_register_info (mod->ebl, -1, NULL, 0, local
77 for (int regno = 0; regno < nregs && likely (result == 0); ++regno)
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/
H A Dr600.h116 unsigned nregs; member in struct:r600_pipe_state
234 state->regs[state->nregs].value = value;
235 state->nregs++;
H A Dr600_state_common.c465 for (int i = 0; i < rstate->nregs; i++) {
1189 rctx->vgt.nregs = 0;
1201 rctx->vgt.nregs = 0;
1388 state->regs[state->nregs].block = block;
1389 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1391 state->regs[state->nregs].value = value;
1392 state->regs[state->nregs].bo = bo;
1393 state->regs[state->nregs].bo_usage = usage;
1395 state->nregs++;
1396 assert(state->nregs < R600_BLOCK_MAX_RE
[all...]
H A Dr600_state.c649 state.nregs = 0;
2130 rstate.nregs = 0;
2472 rstate->nregs = 0;
2589 rstate->nregs = 0;
2638 rstate->nregs = 0;
2725 rstate.nregs = 0;
H A Dr600_hw_context.c759 for (i = 0; i < state->nregs; i++) {
769 for (i = 0; i < state->nregs; i++) {
781 for (int i = 0; i < state->nregs; i++) {
/external/mesa3d/src/gallium/drivers/r600/
H A Dr600.h116 unsigned nregs; member in struct:r600_pipe_state
234 state->regs[state->nregs].value = value;
235 state->nregs++;
H A Dr600_state_common.c465 for (int i = 0; i < rstate->nregs; i++) {
1189 rctx->vgt.nregs = 0;
1201 rctx->vgt.nregs = 0;
1388 state->regs[state->nregs].block = block;
1389 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1391 state->regs[state->nregs].value = value;
1392 state->regs[state->nregs].bo = bo;
1393 state->regs[state->nregs].bo_usage = usage;
1395 state->nregs++;
1396 assert(state->nregs < R600_BLOCK_MAX_RE
[all...]
H A Dr600_state.c649 state.nregs = 0;
2130 rstate.nregs = 0;
2472 rstate->nregs = 0;
2589 rstate->nregs = 0;
2638 rstate->nregs = 0;
2725 rstate.nregs = 0;
H A Dr600_hw_context.c759 for (i = 0; i < state->nregs; i++) {
769 for (i = 0; i < state->nregs; i++) {
781 for (int i = 0; i < state->nregs; i++) {
/external/elfutils/0.153/libdw/
H A Ddwarf_frame_register.c78 if (unlikely ((size_t) regno >= fs->nregs))
H A Dcfi.c69 size_t size = offsetof (Dwarf_Frame, regs[original->nregs]);
102 if (fs->nregs <= reg)
113 bigger->nregs = reg + 1;
308 if (cie->initial_state->nregs > operand)
H A Dcfi.h206 size_t nregs; member in struct:Dwarf_Frame_s
/external/qemu/target-arm/
H A Dop_helper.c483 int nregs; member in struct:__anon30112
505 const int nregs = neon_ls_element_type[op].nregs; local
513 for (reg = 0; reg < nregs; reg++) {
514 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
516 } else if (interleave == 2 && nregs == 4 && reg == 2) {
H A Dhelper.c365 int nregs; local
368 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
369 if (reg < nregs) {
375 nregs += 16;
376 if (reg < nregs) {
382 switch (reg - nregs) {
392 int nregs; local
394 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
395 if (reg < nregs) {
400 nregs
[all...]
H A Dtranslate.c3884 int nregs; member in struct:__anon30113
3907 int nregs; local
3947 nregs = neon_ls_element_type[op].nregs;
3956 stride = nregs * 8;
3966 nregs = ((insn >> 8) & 3) + 1;
3969 if (nregs != 4 || a == 0) {
3975 if (nregs == 1 && a == 1 && size == 0) {
3978 if (nregs == 3 && a == 1) {
3983 if (nregs
[all...]
/external/elfutils/0.153/backends/
H A Dia64_retval.c100 inline int hfa (const Dwarf_Op *loc, int nregs) argument
106 return fpregs_used + nregs;
/external/jemalloc/src/
H A Dstats.c87 uint32_t nregs; local
106 CTL_J_GET("arenas.bin.0.nregs", &nregs, uint32_t);
132 j, reg_size, nregs, run_size / page,
140 j, reg_size, nregs, run_size / page,
H A Dtcache.c494 if ((arena_bin_info[i].nregs << 1) <= TCACHE_NSLOTS_SMALL_MAX) {
496 (arena_bin_info[i].nregs << 1);
H A Darena.c329 assert(run->nfree < bin_info->nregs);
1481 run->nfree = bin_info->nregs;
1539 if (run->nfree == bin_info->nregs)
1884 if (bin_info->nregs != 1) {
1990 if (run->nfree == bin_info->nregs) {
2464 * *) bin_info->nregs <= RUN_MAXREGS
2466 * bin_info->nregs, bin_info->bitmap_offset, and bin_info->reg0_offset are also
2576 bin_info->nregs = good_nregs;
2580 assert(bin_info->reg0_offset - bin_info->redzone_size + (bin_info->nregs
2596 bitmap_info_init(&bin_info->bitmap_info, bin_info->nregs);
[all...]
/external/jemalloc/test/unit/
H A Dmallctl.c109 assert_d_eq(mallctlnametomib("arenas.bin.0.nregs", mib, &miblen), 0,
329 TEST_ARENAS_BIN_CONSTANT(uint32_t, nregs, arena_bin_info[0].nregs);
/external/valgrind/main/VEX/priv/
H A Dhost_amd64_defs.h557 /* Do 'ffree' on %st(7) .. %st(7-nregs) */
559 Int nregs; /* 1 <= nregs <= 7 */ member in struct:__anon31681::__anon31682::__anon31707
723 extern AMD64Instr* AMD64Instr_A87Free ( Int nregs );
H A Dhost_amd64_defs.c135 void getAllocableRegs_AMD64 ( Int* nregs, HReg** arr ) argument
138 *nregs = 6;
139 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
149 *nregs = 20;
150 *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
813 AMD64Instr* AMD64Instr_A87Free ( Int nregs )
817 i->Ain.A87Free.nregs = nregs;
818 vassert(nregs >= 1 && nregs <
[all...]
/external/jemalloc/include/jemalloc/internal/
H A Darena.h199 /* Index of next region that has never been allocated, or nregs. */
232 * | region nregs-1 |
256 uint32_t nregs; member in struct:arena_bin_info_s
1018 assert(regind < bin_info->nregs);
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.c305 rstate.nregs = 0;

Completed in 385 milliseconds

12