/external/linux-tools-perf/perf-3.12.0/arch/arm/lib/ |
H A D | memcpy.S | 23 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort 24 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4} 27 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 28 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} 39 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort 40 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
|
/external/valgrind/main/none/tests/s390x/ |
H A D | cksm.c | 27 register uint64_t reg3 asm("3") = len; 33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory"); 36 len = reg3;
|
/external/pixman/pixman/ |
H A D | pixman-android-neon.S | 93 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2 98 bilinear_load_8888 reg3, reg4, tmp2 99 vmull.u8 acc2, reg3, d28
|
H A D | pixman-arm-neon-asm.h | 92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits variable 94 op&.&elem_size {d®1, d®2, d®3, d®4}, [&mem_operand&, :&abits&]! variable 96 op&.&elem_size {d®1, d®2, d®3, d®4}, [&mem_operand&]! variable 104 .macro pixldst3 op, elem_size, reg1, reg2, reg3, mem_operand variable 105 op&.&elem_size {d®1, d®2, d®3}, [&mem_operand&]! 108 .macro pixldst30 op, elem_size, reg1, reg2, reg3, idx, mem_operand variable 109 op&.&elem_size {d®1[idx], d®2[idx], d®3[idx]}, [&mem_operand&]!
|
H A D | pixman-arm-simd-asm.h | 99 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0 variable 105 op&r&cond WK®3, [base], #4 variable 107 op&m&cond&ia base!, {WK®0,WK®1,WK®2,WK®3} 127 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base variable 129 stm&cond&db base, {WK®0,WK®1,WK®2,WK®3}
|
H A D | pixman-arm-neon-asm-bilinear.S | 109 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2 114 bilinear_load_8888 reg3, reg4, tmp2 115 vmull.u8 acc2, reg3, d28 130 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi 142 convert_0565_to_x888 acc2, reg3, reg2, reg1 143 vzip.u8 reg1, reg3 145 vzip.u8 reg3, reg4 149 vmull.u8 acc2, reg3, d28
|
H A D | pixman-arm-simd-asm.S | 374 .macro over_8888_8888_check_transparent numbytes, reg0, reg1, reg2, reg3 381 teqeq WK®3, #0
|
H A D | pixman-arm-neon-asm.S | 2868 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2 2873 bilinear_load_8888 reg3, reg4, tmp2 2874 vmull.u8 acc2, reg3, d28 2889 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi 2901 convert_0565_to_x888 acc2, reg3, reg2, reg1 2902 vzip.u8 reg1, reg3 2904 vzip.u8 reg3, reg4 2908 vmull.u8 acc2, reg3, d28
|
/external/vixl/src/a64/ |
H A D | macro-assembler-a64.cc | 1416 const Register& reg3, 1418 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); 1428 const FPRegister& reg3, 1430 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); 1447 const Register& reg3, 1449 RegList exclude = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); 1456 const FPRegister& reg3, 1458 RegList excludefp = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); 1465 const CPURegister& reg3, 1470 const CPURegister regs[] = {reg1, reg2, reg3, reg [all...] |
H A D | assembler-a64.h | 283 const CPURegister& reg3 = NoReg, 297 const CPURegister& reg3 = NoCPUReg, 310 CPURegister reg3 = NoCPUReg, 312 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()), 314 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
|
H A D | macro-assembler-a64.h | 1321 const Register& reg3 = NoReg, 1325 const FPRegister& reg3 = NoFPReg, 1335 const Register& reg3 = NoReg, 1339 const FPRegister& reg3 = NoFPReg, 1343 const CPURegister& reg3 = NoCPUReg,
|
H A D | assembler-a64.cc | 2246 const CPURegister& reg3, const CPURegister& reg4, 2255 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; 2283 const CPURegister& reg3, const CPURegister& reg4, 2289 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1); 2245 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument 2282 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
|
/external/chromium_org/third_party/skia/gm/ |
H A D | bitmaprect.cpp | 254 static skiagm::GMRegistry reg3(MyFactory3);
|
H A D | glyph_pos.cpp | 198 static GMRegistry reg3(GlyphPosHairlineStrokeFactory);
|
H A D | gradients.cpp | 450 static GMRegistry reg3(MyFactory3);
|
H A D | gradients_2pt_conical.cpp | 373 static GMRegistry reg3(MyFactory3);
|
/external/skia/gm/ |
H A D | bitmaprect.cpp | 247 static skiagm::GMRegistry reg3(MyFactory3);
|
H A D | gradients.cpp | 454 static GMRegistry reg3(MyFactory3);
|
H A D | gradients_2pt_conical.cpp | 380 static GMRegistry reg3(MyFactory3);
|
/external/chromium_org/v8/src/arm64/ |
H A D | assembler-arm64.h | 412 Register reg3 = NoReg, 420 const CPURegister& reg3 = NoReg, 433 const CPURegister& reg3 = NoCPUReg, 450 CPURegister reg3 = NoCPUReg, 452 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()), 454 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
|
H A D | assembler-arm64.cc | 207 Register reg3, Register reg4) { 208 CPURegList regs(reg1, reg2, reg3, reg4); 220 const CPURegister& reg3, const CPURegister& reg4, 229 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; 257 const CPURegister& reg3, const CPURegister& reg4, 263 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1); 206 GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4) argument 219 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument 256 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
|
/external/chromium_org/third_party/sqlite/src/src/ |
H A D | build.c | 865 int reg1, reg2, reg3; local 879 reg3 = ++pParse->nMem; 880 sqlite3VdbeAddOp3(v, OP_ReadCookie, iDb, reg3, BTREE_FILE_FORMAT); 882 j1 = sqlite3VdbeAddOp1(v, OP_If, reg3); 885 sqlite3VdbeAddOp2(v, OP_Integer, fileFormat, reg3); 886 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_FILE_FORMAT, reg3); 887 sqlite3VdbeAddOp2(v, OP_Integer, ENC(db), reg3); 888 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_TEXT_ENCODING, reg3); 910 sqlite3VdbeAddOp2(v, OP_Null, 0, reg3); 911 sqlite3VdbeAddOp3(v, OP_Insert, 0, reg3, reg [all...] |
/external/chromium_org/third_party/libvpx/source/libvpx/vp9/common/arm/neon/ |
H A D | vp9_idct32x32_add_neon.asm | 241 DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4 278 vqrshrn.s32 $reg3, q11, #14 286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4 287 DO_BUTTERFLY d28, d29, d26, d27, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
|
/external/libvpx/libvpx/vp9/common/arm/neon/ |
H A D | vp9_idct32x32_add_neon.asm | 241 DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4 278 vqrshrn.s32 $reg3, q11, #14 286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4 287 DO_BUTTERFLY d28, d29, d26, d27, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
|
/external/chromium_org/v8/src/arm/ |
H A D | macro-assembler-arm.cc | 3947 Register reg3, 3954 if (reg3.is_valid()) regs |= reg3.bit(); 3998 Register reg3, 4005 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + 4011 if (reg3.is_valid()) regs |= reg3.bit();
|