Searched refs:reg_width (Results 1 - 15 of 15) sorted by relevance

/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_fs_reg_allocate.cpp34 assign_reg(int *reg_hw_locations, fs_reg *reg, int reg_width) argument
38 reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset * reg_width;
48 int reg_width = c->dispatch_width / 8; local
51 hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width);
54 this->virtual_grf_sizes[i - 1] * reg_width);
61 assign_reg(hw_reg_mapping, &inst->dst, reg_width);
62 assign_reg(hw_reg_mapping, &inst->src[0], reg_width);
63 assign_reg(hw_reg_mapping, &inst->src[1], reg_width);
64 assign_reg(hw_reg_mapping, &inst->src[2], reg_width);
78 int reg_width,
75 brw_alloc_reg_set_for_classes(struct brw_context *brw, int *class_sizes, int class_count, int reg_width, int base_reg_count) argument
157 int reg_width = c->dispatch_width / 8; local
[all...]
H A Dbrw_fs_visitor.cpp924 int reg_width = c->dispatch_width / 8; local
938 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
955 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
960 mlen += vector_elements * reg_width;
963 mlen = MAX2(mlen, header_present + 4 * reg_width);
966 mlen += reg_width;
975 mlen = MAX2(mlen, header_present + 4 * reg_width);
977 mlen += reg_width;
982 mlen = MAX2(mlen, header_present + 4 * reg_width);
984 mlen += reg_width;
1044 int reg_width = c->dispatch_width / 8; local
1836 int reg_width = c->dispatch_width / 8; local
1959 int reg_width = c->dispatch_width / 8; local
2043 int reg_width = c->dispatch_width / 8; local
[all...]
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_fs_reg_allocate.cpp34 assign_reg(int *reg_hw_locations, fs_reg *reg, int reg_width) argument
38 reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset * reg_width;
48 int reg_width = c->dispatch_width / 8; local
51 hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width);
54 this->virtual_grf_sizes[i - 1] * reg_width);
61 assign_reg(hw_reg_mapping, &inst->dst, reg_width);
62 assign_reg(hw_reg_mapping, &inst->src[0], reg_width);
63 assign_reg(hw_reg_mapping, &inst->src[1], reg_width);
64 assign_reg(hw_reg_mapping, &inst->src[2], reg_width);
78 int reg_width,
75 brw_alloc_reg_set_for_classes(struct brw_context *brw, int *class_sizes, int class_count, int reg_width, int base_reg_count) argument
157 int reg_width = c->dispatch_width / 8; local
[all...]
H A Dbrw_fs_visitor.cpp924 int reg_width = c->dispatch_width / 8; local
938 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
955 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
960 mlen += vector_elements * reg_width;
963 mlen = MAX2(mlen, header_present + 4 * reg_width);
966 mlen += reg_width;
975 mlen = MAX2(mlen, header_present + 4 * reg_width);
977 mlen += reg_width;
982 mlen = MAX2(mlen, header_present + 4 * reg_width);
984 mlen += reg_width;
1044 int reg_width = c->dispatch_width / 8; local
1836 int reg_width = c->dispatch_width / 8; local
1959 int reg_width = c->dispatch_width / 8; local
2043 int reg_width = c->dispatch_width / 8; local
[all...]
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
H A Dradeon_blit.c260 float reg_width, float reg_height,
264 buf[1] = buf[0] + reg_width / img_width;
278 unsigned reg_width, unsigned reg_height,
287 reg_width, reg_height,
295 verts[4] = dst_x_offset + reg_width;
300 verts[8] = dst_x_offset + reg_width;
358 unsigned reg_width,
375 if (reg_width + src_x_offset > src_width)
376 reg_width = src_width - src_x_offset;
379 if (reg_width
258 calc_tex_coords(float img_width, float img_height, float x, float y, float reg_width, float reg_height, unsigned flip_y, float *buf) argument
274 emit_draw_packet(struct r100_context *r100, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
341 r100_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, gl_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, gl_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
[all...]
H A Dradeon_common_context.h495 unsigned reg_width,
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_blit.c260 float reg_width, float reg_height,
264 buf[1] = buf[0] + reg_width / img_width;
278 unsigned reg_width, unsigned reg_height,
287 reg_width, reg_height,
295 verts[4] = dst_x_offset + reg_width;
300 verts[8] = dst_x_offset + reg_width;
358 unsigned reg_width,
375 if (reg_width + src_x_offset > src_width)
376 reg_width = src_width - src_x_offset;
379 if (reg_width
258 calc_tex_coords(float img_width, float img_height, float x, float y, float reg_width, float reg_height, unsigned flip_y, float *buf) argument
274 emit_draw_packet(struct r100_context *r100, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
341 r100_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, gl_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, gl_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
[all...]
H A Dradeon_common_context.h495 unsigned reg_width,
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIGenRegisterInfo.pl248 my ($reg_width, $sub_reg_ref, @types) = @_;
249 return print_reg_class('SReg', 'SGPR', $reg_width, $SGPR_COUNT, $sub_reg_ref, @types);
253 my ($reg_width, $sub_reg_ref, @types) = @_;
254 return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types);
258 my ($class_prefix, $reg_prefix, $reg_width, $reg_count, $sub_reg_ref, @types) = @_;
260 my $component_count = $reg_width / 32;
263 my $reg_name = $reg_prefix . $i . '_' . $reg_width;
269 print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n";
274 if ($class_prefix eq 'SReg' and $reg_width == 64) {
279 if ($class_prefix eq 'SReg' and $reg_width
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIGenRegisterInfo.pl248 my ($reg_width, $sub_reg_ref, @types) = @_;
249 return print_reg_class('SReg', 'SGPR', $reg_width, $SGPR_COUNT, $sub_reg_ref, @types);
253 my ($reg_width, $sub_reg_ref, @types) = @_;
254 return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types);
258 my ($class_prefix, $reg_prefix, $reg_width, $reg_count, $sub_reg_ref, @types) = @_;
260 my $component_count = $reg_width / 32;
263 my $reg_name = $reg_prefix . $i . '_' . $reg_width;
269 print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n";
274 if ($class_prefix eq 'SReg' and $reg_width == 64) {
279 if ($class_prefix eq 'SReg' and $reg_width
[all...]
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
H A Dr200_blit.c385 float reg_width, float reg_height,
389 buf[1] = buf[0] + reg_width / img_width;
403 unsigned reg_width, unsigned reg_height,
412 reg_width, reg_height,
420 verts[4] = dst_x_offset + reg_width;
425 verts[8] = dst_x_offset + reg_width;
480 unsigned reg_width,
497 if (reg_width + src_x_offset > src_width)
498 reg_width = src_width - src_x_offset;
501 if (reg_width
383 calc_tex_coords(float img_width, float img_height, float x, float y, float reg_width, float reg_height, unsigned flip_y, float *buf) argument
399 emit_draw_packet(struct r200_context *r200, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
463 r200_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, gl_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, gl_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
[all...]
H A Dradeon_common_context.h495 unsigned reg_width,
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_blit.c385 float reg_width, float reg_height,
389 buf[1] = buf[0] + reg_width / img_width;
403 unsigned reg_width, unsigned reg_height,
412 reg_width, reg_height,
420 verts[4] = dst_x_offset + reg_width;
425 verts[8] = dst_x_offset + reg_width;
480 unsigned reg_width,
497 if (reg_width + src_x_offset > src_width)
498 reg_width = src_width - src_x_offset;
501 if (reg_width
383 calc_tex_coords(float img_width, float img_height, float x, float y, float reg_width, float reg_height, unsigned flip_y, float *buf) argument
399 emit_draw_packet(struct r200_context *r200, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
463 r200_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, gl_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, gl_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
[all...]
H A Dradeon_common_context.h495 unsigned reg_width,
/external/vixl/src/a64/
H A Dsimulator-a64.h511 int64_t Rotate(unsigned reg_width,
515 int64_t ExtendValue(unsigned reg_width,

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