| /external/llvm/test/MC/Mips/ |
| H A D | micromips-shift-instructions.s | 17 # CHECK-EL: rotrv $9, $6, $7 # encoding: [0xc7,0x00,0xd0,0x48]
28 # CHECK-EB: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
36 rotrv $9, $6, $7
|
| H A D | mips-alu-instructions.s | 20 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
51 rotrv $9, $6, $7
|
| H A D | mips64-alu-instructions.s | 18 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
46 rotrv $9, $6, $7
|
| /external/chromium_org/v8/test/cctest/ |
| H A D | test-disasm-mips.cc | 365 COMPARE(rotrv(a0, a1, a2),
366 "00c52046 rotrv a0, a1, a2");
367 COMPARE(rotrv(s0, s1, s2),
368 "02518046 rotrv s0, s1, s2");
369 COMPARE(rotrv(t2, t3, t4),
370 "018b5046 rotrv t2, t3, t4");
371 COMPARE(rotrv(v0, v1, fp),
372 "03c31046 rotrv v0, v1, fp");
|
| H A D | test-disasm-mips64.cc | 510 COMPARE(rotrv(a0, a1, a2),
511 "00c52046 rotrv a0, a1, a2");
512 COMPARE(rotrv(s0, s1, s2),
513 "02518046 rotrv s0, s1, s2");
514 COMPARE(rotrv(a6, a7, t0),
515 "018b5046 rotrv a6, a7, t0");
516 COMPARE(rotrv(v0, v1, fp),
517 "03c31046 rotrv v0, v1, fp");
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | invalid-mips64r2.s | 26 rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 28 rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 138 rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | invalid-mips64r2.s | 40 rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 196 rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips32r2.s | 60 rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/chromium_org/v8/src/mips/ |
| H A D | assembler-mips.h | 790 void rotrv(Register rd, Register rt, Register rs);
|
| H A D | assembler-mips.cc | 1645 void Assembler::rotrv(Register rd, Register rt, Register rs) { function in class:v8::Assembler
|
| H A D | macro-assembler-mips.cc | 931 rotrv(rd, rs, rt.rm());
|
| /external/chromium_org/v8/src/mips64/ |
| H A D | assembler-mips64.h | 802 void rotrv(Register rd, Register rt, Register rs);
|
| H A D | assembler-mips64.cc | 1709 void Assembler::rotrv(Register rd, Register rt, Register rs) { function in class:v8::Assembler
|
| H A D | macro-assembler-mips64.cc | 1008 rotrv(rd, rs, rt.rm());
|