/external/valgrind/main/VEX/priv/ |
H A D | host_generic_reg_alloc2.c | 79 HReg rreg; member in struct:__anon31907 95 /* Which rreg is this for? */ 96 HReg rreg; member in struct:__anon31908 106 rreg has the same value as the spill slot for the associated 108 spill store or reload for this rreg. */ 130 rreg" is the main beneficiary. 133 associated with any rreg, that entry can be set to INVALID_RREG_NO. 353 HReg rreg, vreg, vregS, vregD; local 391 /* The vreg -> rreg map constructed and then applied to each 429 (*ppReg)(rreg_state[z].rreg); \ [all...] |
H A D | host_mips_defs.c | 2316 void genSpill_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, argument 2321 vassert(!hregIsVirtual(rreg)); 2325 switch (hregClass(rreg)) { 2328 *i1 = MIPSInstr_Store(8, am, rreg, mode64); 2332 *i1 = MIPSInstr_Store(4, am, rreg, mode64); 2336 *i1 = MIPSInstr_FpLdSt(False /*Store */ , 4, rreg, am); 2339 *i1 = MIPSInstr_FpLdSt(False /*Store */ , 8, rreg, am); 2342 ppHRegClass(hregClass(rreg)); 2348 void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, argument 2352 vassert(!hregIsVirtual(rreg)); [all...] |
H A D | host_amd64_defs.h | 765 HReg rreg, Int offset, Bool ); 767 HReg rreg, Int offset, Bool );
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H A D | host_arm64_defs.h | 1126 HReg rreg, Int offset, Bool ); 1128 HReg rreg, Int offset, Bool );
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H A D | host_arm_defs.h | 1036 HReg rreg, Int offset, Bool ); 1038 HReg rreg, Int offset, Bool );
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H A D | host_mips_defs.h | 714 HReg rreg, Int offset, Bool); 716 HReg rreg, Int offset, Bool);
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H A D | host_x86_defs.h | 726 HReg rreg, Int offset, Bool ); 728 HReg rreg, Int offset, Bool );
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H A D | host_x86_defs.c | 1707 HReg rreg, Int offsetB, Bool mode64 ) 1711 vassert(!hregIsVirtual(rreg)); 1715 switch (hregClass(rreg)) { 1717 *i1 = X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am ); 1720 *i1 = X86Instr_FpLdSt ( False/*store*/, 10, rreg, am ); 1723 *i1 = X86Instr_SseLdSt ( False/*store*/, rreg, am ); 1726 ppHRegClass(hregClass(rreg)); 1732 HReg rreg, Int offsetB, Bool mode64 ) 1736 vassert(!hregIsVirtual(rreg)); 1740 switch (hregClass(rreg)) { 1706 genSpill_X86( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument 1731 genReload_X86( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument [all...] |
H A D | host_amd64_defs.c | 1859 HReg rreg, Int offsetB, Bool mode64 ) 1863 vassert(!hregIsVirtual(rreg)); 1867 switch (hregClass(rreg)) { 1869 *i1 = AMD64Instr_Alu64M ( Aalu_MOV, AMD64RI_Reg(rreg), am ); 1872 *i1 = AMD64Instr_SseLdSt ( False/*store*/, 16, rreg, am ); 1875 ppHRegClass(hregClass(rreg)); 1881 HReg rreg, Int offsetB, Bool mode64 ) 1885 vassert(!hregIsVirtual(rreg)); 1889 switch (hregClass(rreg)) { 1891 *i1 = AMD64Instr_Alu64R ( Aalu_MOV, AMD64RMI_Mem(am), rreg ); 1858 genSpill_AMD64( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument 1880 genReload_AMD64( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument [all...] |
H A D | host_arm64_defs.c | 3225 HReg rreg, Int offsetB, Bool mode64 ) 3229 vassert(!hregIsVirtual(rreg)); 3232 rclass = hregClass(rreg); 3240 rreg, 3248 rreg, hregARM64_X21(), offsetB); 3256 *i2 = ARM64Instr_VLdStQ(False/*!isLoad*/, rreg, x9); 3266 HReg rreg, Int offsetB, Bool mode64 ) 3270 vassert(!hregIsVirtual(rreg)); 3273 rclass = hregClass(rreg); 3281 rreg, 3224 genSpill_ARM64( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument 3265 genReload_ARM64( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument [all...] |
H A D | host_ppc_defs.h | 1147 HReg rreg, Int offsetB, Bool mode64 ); 1149 HReg rreg, Int offsetB, Bool mode64 );
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H A D | host_arm_defs.c | 2571 HReg rreg, Int offsetB, Bool mode64 ) 2575 vassert(!hregIsVirtual(rreg)); 2578 rclass = hregClass(rreg); 2583 rreg, 2603 rreg, 2607 rreg, 2616 *i2 = ARMInstr_NLdStQ(False, rreg, mkARMAModeN_R(r12)); 2626 HReg rreg, Int offsetB, Bool mode64 ) 2630 vassert(!hregIsVirtual(rreg)); 2633 rclass = hregClass(rreg); 2570 genSpill_ARM( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument 2625 genReload_ARM( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument [all...] |
H A D | host_ppc_defs.c | 3027 HReg rreg, Int offsetB, Bool mode64 ) 3030 vassert(!hregIsVirtual(rreg)); 3033 switch (hregClass(rreg)) { 3036 *i1 = PPCInstr_Store( 8, am, rreg, mode64 ); 3040 *i1 = PPCInstr_Store( 4, am, rreg, mode64 ); 3043 *i1 = PPCInstr_FpLdSt ( False/*store*/, 8, rreg, am ); 3048 *i1 = PPCInstr_AvLdSt ( False/*store*/, 16, rreg, am ); 3051 ppHRegClass(hregClass(rreg)); 3057 HReg rreg, Int offsetB, Bool mode64 ) 3060 vassert(!hregIsVirtual(rreg)); 3026 genSpill_PPC( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument 3056 genReload_PPC( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument [all...] |
H A D | host_s390_defs.c | 463 genSpill_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) argument 468 vassert(!hregIsVirtual(rreg)); 474 switch (hregClass(rreg)) { 477 *i1 = s390_insn_store(8, am, rreg); 481 ppHRegClass(hregClass(rreg)); 489 genReload_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) argument 494 vassert(!hregIsVirtual(rreg)); 500 switch (hregClass(rreg)) { 503 *i1 = s390_insn_load(8, rreg, am); 507 ppHRegClass(hregClass(rreg)); [all...] |
/external/chromium_org/third_party/openmax_dl/dl/api/arm/ |
H A D | armCOMM_s.h | 37 .macro _M_GETRREGLIST rreg 38 .ifeqs "\rreg", "" 42 @ If rreg is lr or r4, save lr and r4 43 .ifeqs "\rreg", "lr" 48 .ifeqs "\rreg", "r4" 53 @ If rreg = r5 or r6, save up to register r6 54 .ifeqs "\rreg", "r5" 58 .ifeqs "\rreg", "r6" 63 @ If rreg = r7 or r8, save up to register r8 64 .ifeqs "\rreg", "r 166 .macro M_START name, rreg, dreg variable [all...] |
H A D | arm64COMM_s.h | 81 .warning "Unrecognized saved d register limit: \rreg" 95 // rreg = "" don't stack any registers 104 .macro M_START name, rreg, dreg variable
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