| /external/chromium_org/v8/src/arm/ |
| H A D | disasm-arm.cc | 579 if (format[1] == 'h') { // 'shift_op or 'shift_rm or 'shift_sat.
580 if (format[6] == 'o') { // 'shift_op
581 DCHECK(STRING_STARTS_WITH(format, "shift_op"));
858 Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
862 Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
866 Format(instr, "sub'cond's 'rd, 'rn, 'shift_op");
870 Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op");
874 Format(instr, "add'cond's 'rd, 'rn, 'shift_op");
878 Format(instr, "adc'cond's 'rd, 'rn, 'shift_op");
882 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op");
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| H A D | assembler-arm.cc | 281 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { argument
286 shift_op_ = shift_op;
289 if ((shift_op == ROR) && (shift_imm == 0)) {
292 shift_op = LSL;
293 } else if (shift_op == RRX) {
302 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { argument
303 DCHECK(shift_op != RRX);
306 shift_op_ = shift_op;
329 ShiftOp shift_op, int shift_imm, AddrMode am) {
333 shift_op_ = shift_op;
328 MemOperand(Register rn, Register rm, ShiftOp shift_op, int shift_imm, AddrMode am) argument
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| H A D | assembler-arm.h | 501 // rm <shift_op> shift_imm
502 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
515 // rm <shift_op> rs
516 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
542 ShiftOp shift_op() const { return shift_op_; } function in class:v8::internal::BASE_EMBEDDED
571 // [rn +/- rm <shift_op> shift_imm] Offset/NegOffset
572 // [rn +/- rm <shift_op> shift_imm]! PreIndex/NegPreIndex
573 // [rn], +/- rm <shift_op> shift_imm PostIndex/NegPostIndex
575 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
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| H A D | macro-assembler-arm.cc | 363 DCHECK((src.shift_op() == ASR) || (src.shift_op() == LSL));
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| /external/chromium_org/v8/src/compiler/ |
| H A D | js-typed-lowering.h | 49 const Operator* shift_op);
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| H A D | js-typed-lowering.cc | 282 const Operator* shift_op) {
285 return r.ChangeToPureOperator(shift_op);
281 ReduceI32Shift(Node* node, bool left_signed, const Operator* shift_op) argument
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| /external/vixl/src/a64/ |
| H A D | simulator-a64.cc | 1146 Shift shift_op = NO_SHIFT; local
1198 case LSLV_x: shift_op = LSL; break;
1200 case LSRV_x: shift_op = LSR; break;
1202 case ASRV_x: shift_op = ASR; break;
1204 case RORV_x: shift_op = ROR; break;
1209 if (shift_op != NO_SHIFT) {
1214 result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op,
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| /external/chromium_org/v8/src/arm64/ |
| H A D | lithium-arm64.cc | 2189 Shift shift_op; local
2191 case HValue::kShl: shift_op = LSL; break;
2192 case HValue::kShr: shift_op = LSR; break;
2193 case HValue::kSar: shift_op = ASR; break;
2194 default: UNREACHABLE(); shift_op = NO_SHIFT;
2198 res = new(zone()) LBitI(left, right, shift_op, shift_amount);
2200 res = new(zone()) LAddI(left, right, shift_op, shift_amount);
2203 res = new(zone()) LSubI(left, right, shift_op, shift_amount);
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| H A D | simulator-arm64.cc | 2006 Shift shift_op = NO_SHIFT; local
2037 case LSLV_x: shift_op = LSL; break;
2039 case LSRV_x: shift_op = LSR; break;
2041 case ASRV_x: shift_op = ASR; break;
2043 case RORV_x: shift_op = ROR; break;
2047 if (shift_op != NO_SHIFT) {
2056 result = ShiftOperand(reg<T>(instr->Rn()), shift_op, shift);
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| /external/valgrind/main/VEX/priv/ |
| H A D | guest_arm_toIR.c | 3209 IROp shift_op, add_op; local
3223 shift_op = U ? Iop_ShrN8x16 : Iop_SarN8x16;
3227 shift_op = U ? Iop_ShrN16x8 : Iop_SarN16x8;
3231 shift_op = U ? Iop_ShrN32x4 : Iop_SarN32x4;
3242 shift_op = U ? Iop_ShrN8x8 : Iop_SarN8x8;
3246 shift_op = U ? Iop_ShrN16x4 : Iop_SarN16x4;
3250 shift_op = U ? Iop_ShrN32x2 : Iop_SarN32x2;
3261 assign(cc, binop(shift_op,
3280 binop(shift_op,
3283 binop(shift_op,
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