| /external/llvm/test/MC/Mips/ |
| H A D | micromips-shift-instructions.s | 15 # CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10]
26 # CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
34 srlv $2, $3, $5
|
| H A D | mips-alu-instructions.s | 31 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
62 srlv $2, $3, $5
|
| H A D | mips64-alu-instructions.s | 29 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
57 srlv $2, $3, $5
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | valid.s | 96 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
97 srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/chromium_org/v8/test/cctest/ |
| H A D | test-disasm-mips.cc | 328 COMPARE(srlv(a0, a1, a2),
329 "00c52006 srlv a0, a1, a2");
330 COMPARE(srlv(s0, s1, s2),
331 "02518006 srlv s0, s1, s2");
332 COMPARE(srlv(t2, t3, t4),
333 "018b5006 srlv t2, t3, t4");
334 COMPARE(srlv(v0, v1, fp),
335 "03c31006 srlv v0, v1, fp");
|
| H A D | test-disasm-mips64.cc | 441 COMPARE(srlv(a0, a1, a2),
442 "00c52006 srlv a0, a1, a2");
443 COMPARE(srlv(s0, s1, s2),
444 "02518006 srlv s0, s1, s2");
445 COMPARE(srlv(a6, a7, t0),
446 "018b5006 srlv a6, a7, t0");
447 COMPARE(srlv(v0, v1, fp),
448 "03c31006 srlv v0, v1, fp");
|
| H A D | test-assembler-mips.cc | 147 __ srlv(v0, v0, t0); // 0x0f234560
|
| H A D | test-assembler-mips64.cc | 149 __ srlv(v0, v0, a4); // 0x0f234560
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | valid.s | 112 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
113 srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | valid.s | 140 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
141 srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 168 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
169 srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 170 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
171 srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 188 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
189 srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 189 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
190 srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 205 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
206 srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 232 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
233 srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/chromium_org/v8/src/mips/ |
| H A D | disasm-mips.cc | 663 Format(instr, "srlv 'rd, 'rt, 'rs");
|
| H A D | assembler-mips.h | 786 void srlv(Register rd, Register rt, Register rs);
|
| H A D | assembler-mips.cc | 1620 void Assembler::srlv(Register rd, Register rt, Register rs) { function in class:v8::Assembler
|
| H A D | code-stubs-mips.cc | 257 __ srlv(input_low, input_low, scratch);
|
| H A D | full-codegen-mips.cc | 2394 __ srlv(scratch1, scratch1, scratch2);
|
| /external/chromium_org/v8/src/mips64/ |
| H A D | disasm-mips64.cc | 731 Format(instr, "srlv 'rd, 'rt, 'rs");
|
| H A D | assembler-mips64.h | 798 void srlv(Register rd, Register rt, Register rs);
|
| H A D | assembler-mips64.cc | 1684 void Assembler::srlv(Register rd, Register rt, Register rs) { function in class:v8::Assembler
|
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| H A D | memcpy.S | 151 #define SRLV srlv
|