Searched refs:swl (Results 1 - 25 of 35) sorted by relevance

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/external/llvm/test/MC/Mips/
H A Dmicromips-loadstore-unaligned.s14 # CHECK-EL: swl $4, 16($5) # encoding: [0x85,0x60,0x10,0x80]
21 # CHECK-EB: swl $4, 16($5) # encoding: [0x60,0x85,0x80,0x10]
25 swl $4, 16($5)
H A Dmips-memory-instructions.s13 # CHECK: swl $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa8]
20 swl $4, 16($5)
H A Dnacl-mask.s119 swl $4, 0($6)
150 # CHECK-NEXT: swl $4, 0($6)
/external/valgrind/main/none/tests/mips32/
H A DLoadStore.stdout.exp172 swl
173 swl $t0, 0($t1) :: RTval: 0x0, out: 0x0
174 swl $t0, 0($t1) :: RTval: 0x0, out: 0x121f1e00
175 swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x31
176 swl $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e31
177 swl $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7f
178 swl $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121f1e7f
179 swl $t0, 0($t1) :: RTval: 0x80000000, out: 0x80
180 swl $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f1e80
181 swl
[all...]
H A DLoadStore1.stdout.exp172 swl
173 swl $t0, 1($t1) :: RTval: 0x0, out: 0x0
174 swl $t0, 1($t1) :: RTval: 0x0, out: 0x0
175 swl $t0, 3($t1) :: RTval: 0x31415927, out: 0x31000000
176 swl $t0, 3($t1) :: RTval: 0x31415927, out: 0x31000000
177 swl $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffff00
178 swl $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffff00
179 swl $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
180 swl $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
181 swl
[all...]
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips1-wrong-error.s12 swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips1-wrong-error.s12 swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
H A Dinvalid-mips3-wrong-error.s18 swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/pixman/pixman/
H A Dpixman-mips-memcpy-asm.S39 # define SWHI swl /* high part is left in big-endian */
46 # define SWLO swl /* low part is left in big-endian */
/external/linux-tools-perf/perf-3.12.0/arch/mips/lib/
H A Dmemset.S16 #define LONG_S_L swl
H A Dmemcpy.S142 #define STOREL swl
/external/llvm/test/MC/Mips/mips1/
H A Dvalid.s107 swl $15,13694($s3)
/external/openssl/crypto/aes/asm/
H A Daes-mips.S292 swl $8,0+3($5)
293 swl $9,4+3($5)
294 swl $10,8+3($5)
295 swl $11,12+3($5)
599 swl $8,0+3($5)
600 swl $9,4+3($5)
601 swl $10,8+3($5)
602 swl $11,12+3($5)
H A Daes-mips.pl410 swl $s0,0+$MSB($out)
411 swl $s1,4+$MSB($out)
412 swl $s2,8+$MSB($out)
413 swl $s3,12+$MSB($out)
747 swl $s0,0+$MSB($out)
748 swl $s1,4+$MSB($out)
749 swl $s2,8+$MSB($out)
750 swl $s3,12+$MSB($out)
1605 # convert lwl/lwr and swr/swl to little-endian order
/external/llvm/test/MC/Mips/mips2/
H A Dvalid.s123 swl $15,13694($s3)
/external/llvm/test/MC/Mips/mips32/
H A Dvalid.s150 swl $15,13694($s3)
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s179 swl $15,13694($s3)
/external/chromium_org/v8/src/mips/
H A Ddisasm-mips.cc1200 Format(instr, "swl 'rt, 'imm16s('rs)");
/external/chromium_org/v8/src/mips64/
H A Ddisasm-mips64.cc1346 Format(instr, "swl 'rt, 'imm16s('rs)");
/external/chromium_org/v8/test/cctest/
H A Dtest-assembler-mips.cc890 __ swl(t0, MemOperand(a0, OFFSET_OF(T, swl_0)) );
895 __ swl(t1, MemOperand(a0, OFFSET_OF(T, swl_1) + 1) );
900 __ swl(t2, MemOperand(a0, OFFSET_OF(T, swl_2) + 2) );
905 __ swl(t3, MemOperand(a0, OFFSET_OF(T, swl_3) + 3) );
H A Dtest-assembler-mips64.cc924 __ swl(a4, MemOperand(a0, OFFSET_OF(T, swl_0)));
929 __ swl(a5, MemOperand(a0, OFFSET_OF(T, swl_1) + 1));
934 __ swl(a6, MemOperand(a0, OFFSET_OF(T, swl_2) + 2));
939 __ swl(a7, MemOperand(a0, OFFSET_OF(T, swl_3) + 3));
/external/qemu/target-mips/
H A Dhelper.h15 DEF_HELPER_4(swl, void, env, tl, tl, int)
/external/llvm/test/MC/Mips/mips3/
H A Dvalid.s180 swl $15,13694($s3)
/external/llvm/test/MC/Mips/mips4/
H A Dvalid.s198 swl $15,13694($s3)
/external/llvm/test/MC/Mips/mips5/
H A Dvalid.s200 swl $15,13694($s3)

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