| /external/llvm/test/MC/Mips/ |
| H A D | micromips-loadstore-unaligned.s | 15 # CHECK-EL: swr $4, 16($5) # encoding: [0x85,0x60,0x10,0x90]
22 # CHECK-EB: swr $4, 16($5) # encoding: [0x60,0x85,0x90,0x10]
26 swr $4, 16($5)
|
| H A D | nacl-mask.s | 120 swr $4, 0($7)
153 # CHECK-NEXT: swr $4, 0($7)
|
| /external/valgrind/main/none/tests/mips32/ |
| H A D | LoadStore.stdout.exp | 229 swr
230 swr $t0, 0($t1) :: RTval: 0x0, out: 0x0
231 swr $t0, 0($t1) :: RTval: 0x0, out: 0x0
232 swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
233 swr $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
234 swr $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
235 swr $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
236 swr $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
237 swr $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
238 swr
[all...] |
| H A D | LoadStore1.stdout.exp | 229 swr
230 swr $t0, 1($t1) :: RTval: 0x0, out: 0x0
231 swr $t0, 1($t1) :: RTval: 0x0, out: 0x1e1f00
232 swr $t0, 3($t1) :: RTval: 0x31415927, out: 0x27000000
233 swr $t0, 3($t1) :: RTval: 0x31415927, out: 0x27000000
234 swr $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xff000000
235 swr $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xff000000
236 swr $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
237 swr $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
238 swr
[all...] |
| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips1-wrong-error.s | 13 swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips1-wrong-error.s | 13 swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| H A D | invalid-mips3-wrong-error.s | 19 swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/pixman/pixman/ |
| H A D | pixman-mips-memcpy-asm.S | 41 # define SWLO swr /* low part is right in big-endian */
44 # define SWHI swr /* high part is right in little-endian */
|
| /external/linux-tools-perf/perf-3.12.0/arch/mips/lib/ |
| H A D | memset.S | 17 #define LONG_S_R swr
|
| H A D | memcpy.S | 143 #define STORER swr
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | valid.s | 108 swr $s1,-26590($14)
|
| /external/openssl/crypto/aes/asm/ |
| H A D | aes-mips.S | 288 swr $8,0+0($5)
289 swr $9,4+0($5)
290 swr $10,8+0($5)
291 swr $11,12+0($5)
595 swr $8,0+0($5)
596 swr $9,4+0($5)
597 swr $10,8+0($5)
598 swr $11,12+0($5)
|
| H A D | aes-mips.pl | 406 swr $s0,0+$LSB($out)
407 swr $s1,4+$LSB($out)
408 swr $s2,8+$LSB($out)
409 swr $s3,12+$LSB($out)
743 swr $s0,0+$LSB($out)
744 swr $s1,4+$LSB($out)
745 swr $s2,8+$LSB($out)
746 swr $s3,12+$LSB($out)
1605 # convert lwl/lwr and swr/swl to little-endian order
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | valid.s | 124 swr $s1,-26590($14)
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | valid.s | 151 swr $s1,-26590($14)
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 180 swr $s1,-26590($14)
|
| /external/chromium_org/v8/src/mips/ |
| H A D | disasm-mips.cc | 1206 Format(instr, "swr 'rt, 'imm16s('rs)");
|
| /external/chromium_org/v8/test/cctest/ |
| H A D | test-assembler-mips.cc | 911 __ swr(t0, MemOperand(a0, OFFSET_OF(T, swr_0)) );
916 __ swr(t1, MemOperand(a0, OFFSET_OF(T, swr_1) + 1) );
921 __ swr(t2, MemOperand(a0, OFFSET_OF(T, swr_2) + 2) );
926 __ swr(t3, MemOperand(a0, OFFSET_OF(T, swr_3) + 3) );
|
| H A D | test-assembler-mips64.cc | 945 __ swr(a4, MemOperand(a0, OFFSET_OF(T, swr_0)));
950 __ swr(a5, MemOperand(a0, OFFSET_OF(T, swr_1) + 1));
955 __ swr(a6, MemOperand(a0, OFFSET_OF(T, swr_2) + 2));
960 __ swr(a7, MemOperand(a0, OFFSET_OF(T, swr_3) + 3));
|
| /external/qemu/target-mips/ |
| H A D | helper.h | 16 DEF_HELPER_4(swr, void, env, tl, tl, int)
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 181 swr $s1,-26590($14)
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 199 swr $s1,-26590($14)
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 201 swr $s1,-26590($14)
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 217 swr $s1,-26590($14)
|
| /external/chromium_org/v8/src/mips64/ |
| H A D | codegen-mips64.cc | 146 __ swr(t8, MemOperand(a0));
304 __ swr(v1, MemOperand(a0));
|