Searched refs:tcg (Results 1 - 11 of 11) sorted by relevance
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
H A D | r200_state_init.c | 707 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 ); 807 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2); 1197 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff; 1198 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] = 1205 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0; 1206 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = 1213 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
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H A D | r200_texstate.c | 1203 tgi = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] & ~(R200_TEXGEN_INPUT_MASK << 1205 tgcm = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] & ~(R200_TEXGEN_COMP_MASK << 1351 if (tgi != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] || 1352 tgcm != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2]) 1354 R200_STATECHANGE(rmesa, tcg); 1355 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = tgi; 1356 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = tgcm;
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H A D | r200_context.h | 494 struct radeon_state_atom tcg; member in struct:r200_hw_state
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H A D | r200_cmdbuf.c | 77 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg );
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H A D | r200_state.c | 2158 GLuint tpc = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0]; 2200 if (tpc != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0]) { 2201 R200_STATECHANGE(rmesa, tcg); 2202 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = tpc;
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | r200_state_init.c | 707 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 ); 807 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2); 1197 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff; 1198 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] = 1205 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0; 1206 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = 1213 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
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H A D | r200_texstate.c | 1203 tgi = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] & ~(R200_TEXGEN_INPUT_MASK << 1205 tgcm = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] & ~(R200_TEXGEN_COMP_MASK << 1351 if (tgi != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] || 1352 tgcm != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2]) 1354 R200_STATECHANGE(rmesa, tcg); 1355 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = tgi; 1356 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = tgcm;
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H A D | r200_context.h | 494 struct radeon_state_atom tcg; member in struct:r200_hw_state
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H A D | r200_cmdbuf.c | 77 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg );
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H A D | r200_state.c | 2158 GLuint tpc = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0]; 2200 if (tpc != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0]) { 2201 R200_STATECHANGE(rmesa, tcg); 2202 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = tpc;
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/external/qemu/tcg/ |
H A D | tcg.h | 30 #include "tcg-target.h" 39 # error Unknown pointer size for tcg target 57 #include "tcg-runtime.h" 126 #include "tcg-opc.h" 528 /* The TCGBackendData structure is private to tcg-target.c. */ 659 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ 775 /* Value zero-extended to tcg register size. */ 791 /* Value sign-extended to tcg register size. */
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