Searched refs:wreg (Results 1 - 11 of 11) sorted by relevance

/external/vixl/examples/
H A Dswap-int32.cc84 simulator.wreg(0), simulator.wreg(1));
91 simulator.wreg(0), simulator.wreg(1));
H A Dsum-array.cc86 printf("%d = %d\n", data[i], simulator.wreg(0));
/external/vixl/src/a64/
H A Dsimulator-a64.cc576 case CBZ_w: take_branch = (wreg(rt) == 0); break;
578 case CBNZ_w: take_branch = (wreg(rt) != 0); break;
880 MemoryWrite32(address, wreg(rt));
881 MemoryWrite32(address + kWRegSizeInBytes, wreg(rt2));
1039 : wreg(reg_code);
1085 case RBIT_w: set_wreg(dst, ReverseBits(wreg(src), kWRegSize)); break;
1087 case REV16_w: set_wreg(dst, ReverseBytes(wreg(src), Reverse16)); break;
1089 case REV_w: set_wreg(dst, ReverseBytes(wreg(src), Reverse32)); break;
1092 case CLZ_w: set_wreg(dst, CountLeadingZeros(wreg(src), kWRegSize)); break;
1095 set_wreg(dst, CountLeadingSignBits(wreg(sr
[all...]
H A Dsimulator-a64.h233 inline int32_t wreg(unsigned code,
/external/chromium_org/v8/src/arm64/
H A Dsimulator-arm64.cc663 TraceSim("Arguments: %f, %d\n", dreg(0), wreg(0));
664 double result = target(dreg(0), wreg(0));
1352 case CBZ_w: take_branch = (wreg(rt) == 0); break;
1354 case CBNZ_w: take_branch = (wreg(rt) != 0); break;
1401 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
1424 int32_t op2 = ExtendValue(wreg(instr->Rm()), ext, left_shift);
1448 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount);
1497 ConditionalCompareHelper(instr, wreg(instr->Rm()));
1602 case STRB_w: MemoryWrite<uint8_t>(address, wreg(srcdst)); break;
1603 case STRH_w: MemoryWrite<uint16_t>(address, wreg(srcds
[all...]
H A Dsimulator-arm64.h342 int32_t wreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
/external/chromium_org/v8/test/cctest/
H A Dtest-utils-arm64.h58 inline int32_t wreg(unsigned code) const { function in class:RegisterDump
H A Dtest-utils-arm64.cc107 uint32_t result_w = core->wreg(reg.code());
/external/vixl/test/
H A Dtest-utils-a64.h61 inline int32_t wreg(unsigned code) const { function in class:vixl::RegisterDump
H A Dtest-utils-a64.cc107 uint32_t result_w = core->wreg(reg.code());
/external/vixl/test/examples/
H A Dtest-examples.cc361 assert(regs.wreg(0) == y);
362 assert(regs.wreg(1) == x);

Completed in 149 milliseconds