/external/clang/lib/CodeGen/ |
H A D | CGCall.h | 69 /// A value to "use" after the writeback, or null. 93 Writeback writeback; local 94 writeback.Source = srcLV; 95 writeback.Temporary = temporary; 96 writeback.ToUse = toUse; 97 Writebacks.push_back(writeback);
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H A D | CGCall.cpp | 2012 /// Emit the actual writing-back of a writeback. 2014 const CallArgList::Writeback &writeback) { 2015 const LValue &srcLV = writeback.Source; 2018 "shouldn't have writeback for provably null argument"); 2026 llvm::BasicBlock *writebackBB = CGF.createBasicBlock("icr.writeback"); 2034 // Load the value to writeback. 2035 llvm::Value *value = CGF.Builder.CreateLoad(writeback.Temporary); 2040 "icr.writeback-cast"); 2042 // Perform the writeback. 2049 if (writeback 2013 emitWriteback(CodeGenFunction &CGF, const CallArgList::Writeback &writeback) argument [all...] |
/external/llvm/test/MC/ARM/ |
H A D | thumb-diagnostics.s | 56 @ Invalid writeback and register lists for LDM 65 @ CHECK-ERRORS: error: writeback operator '!' expected 68 @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list 71 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list 74 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list 78 @ Invalid writeback and register lists for PUSH/POP 89 @ Invalid writeback and register lists for STM 100 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list 103 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
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H A D | diagnostics.s | 460 @ CHECK-ERRORS: error: writeback register not allowed in register list 461 @ CHECK-ERRORS: error: writeback register not allowed in register list 462 @ CHECK-ERRORS: error: writeback register not allowed in register list 463 @ CHECK-ERRORS: error: writeback register not allowed in register list 484 @ CHECK-ERRORS: error: system STM cannot have writeback register 485 @ CHECK-ERRORS: error: writeback register only allowed on system LDM if PC in register-list
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/external/llvm/test/MC/AArch64/ |
H A D | arm64-diags.s | 155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions 173 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination 176 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination 179 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination 182 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination 188 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source 191 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source 194 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source 197 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source 200 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback bas [all...] |
/external/kernel-headers/original/uapi/drm/ |
H A D | exynos_drm.h | 198 * @writeback: flag of writeback supporting. 215 __u32 writeback; member in struct:drm_exynos_ipp_prop_list
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/external/oprofile/events/i386/nehalem/ |
H A D | unit_masks | 332 0x10 l1d_wb Counts L1D writeback operations to the L2 333 0x20 fill Counts L2 cache line fill operations due to load, RFO, L1D writeback or prefetch 334 0x40 wb Counts L2 writeback operations to the LLC
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/external/oprofile/events/mips/sb1/ |
H A D | events | 48 event:0xd counters:1,2,3 um:zero minimum:500 name:VICTIM_WRITEBACK :A writeback occurs due to replacement
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/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1482 // On stores, the writeback operand precedes Rt. 1502 // On loads, the writeback operand comes after Rt. 1526 bool writeback = (P == 0) || (W == 1); local 1528 if (P && writeback) 1530 else if (!P && writeback) 1533 if (writeback && (Rn == 15 || Rn == Rt)) 1633 bool writeback = (W == 1) | (P == 0); local 1655 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1669 if (writeback && (Rn == 15 || Rn == Rt)) 1686 if (!type && writeback 4765 bool writeback = (W == 1) | (P == 0); local 4802 bool writeback = (W == 1) | (P == 0); local [all...] |
/external/oprofile/events/i386/westmere/ |
H A D | unit_masks | 171 0x10 l1d_wb L1D writeback to L2 transactions 173 0x40 wb L2 writeback to LLC transactions
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/external/oprofile/events/i386/atom/ |
H A D | events | 46 event:0x67 counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_WB : Explicit writeback bus transactions
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/external/qemu/disas/ |
H A D | arm.c | 3459 bfd_boolean writeback = false, postind = false; local 3489 writeback = true; 3494 writeback = true; 3518 func (stream, writeback ? "]!" : "]");
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/external/oprofile/events/x86-64/family11h/ |
H A D | events | 61 event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 fill/writeback
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/external/oprofile/events/x86-64/hammer/ |
H A D | events | 61 event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 fill/writeback
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/external/qemu/qapi-auto-generated/ |
H A D | qapi-types.h | 3168 bool writeback; member in struct:BlockdevCacheOptions
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H A D | qapi-visit.c | 6230 visit_start_optional(m, obj ? &(*obj)->has_writeback : NULL, "writeback", &err); 6232 visit_type_bool(m, obj ? &(*obj)->writeback : NULL, "writeback", &err);
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/external/qemu/target-arm/ |
H A D | translate.c | 3444 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */ 3477 /* writeback */ 6691 /* Base writeback. */ 6732 /* Base writeback. */ 7370 /* Perform base writeback before the loaded value to 7372 ldrd with base writeback is is undefined if the 8035 /* Base writeback. */ 8109 /* Base writeback. */ 8191 /* Base register writeback. */ 8195 /* Fault if writeback registe 8851 int writeback = 0; local [all...] |
/external/valgrind/main/none/tests/arm/ |
H A D | vfp.stdout.exp | 904 ---- VLDM (Increment After, writeback) ---- 950 ---- VSTM (Increment After, no writeback) ---- 983 ---- VSTM (Increment After, writeback) ----
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