Searched defs:Inst (Results 1 - 25 of 153) sorted by last modified time

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/external/regex-re2/re2/
H A Dprog.h49 // Opcodes for Inst
84 class Inst { class in class:re2::Prog
86 Inst() : out_opcode_(0), out1_(0) { } function in class:re2::Prog::Inst
170 DISALLOW_EVIL_CONSTRUCTORS(Inst);
198 Inst *inst(int id) { return &inst_[id]; }
355 Inst* inst_; // pointer to instruction array
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_debug.cpp295 MCInst Inst; local
305 if (!DisAsm->getInstruction(Inst, Size, memoryObject,
335 Printer->printInst(&Inst, Out, "");
337 Printer->printInst(&Inst, Out);
339 Printer->printInst(&Inst);
350 const MCInstrDesc &TID = TII->get(Inst.getOpcode());
352 const TargetInstrDesc &TID = TII->get(Inst.getOpcode());
360 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
361 const MCOperand &operand = Inst.getOperand(i);
H A Dlp_bld_misc.cpp217 lp_set_load_alignment(LLVMValueRef Inst, argument
220 llvm::unwrap<llvm::LoadInst>(Inst)->setAlignment(Align);
225 lp_set_store_alignment(LLVMValueRef Inst, argument
228 llvm::unwrap<llvm::StoreInst>(Inst)->setAlignment(Align);
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_dataflow.h75 struct rc_instruction * Inst; member in struct:rc_reader
H A Dradeon_pair_schedule.c123 struct rc_instruciont * Inst; member in struct:remap_reg
973 rgb_to_alpha_remap(reader.Inst, reader.U.P.Arg,
H A Dradeon_variable.h48 struct rc_instruction * Inst; member in struct:rc_variable
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUAsmBackend.cpp55 virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const { argument
58 virtual bool mayNeedRelaxation(const MCInst &Inst) const { return false; }
/external/llvm/utils/TableGen/
H A DAsmWriterEmitter.cpp158 const AsmWriterInst *Inst = getAsmWriterInstByID(i); local
159 if (!Inst)
163 if (Inst->Operands.empty())
166 Command = " " + Inst->Operands[0].getCode() + "\n";
175 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
182 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
385 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
386 if (!Inst->Operands.empty()) {
388 assert(NumOps <= Inst->Operands.size() &&
390 Inst
493 AsmWriterInst &Inst = Instructions[i]; local
[all...]
H A DCodeGenDAGPatterns.cpp1659 const DAGInstruction &Inst = CDP.getInstruction(getOperator()); local
1670 MadeChange |= UpdateNodeTypeFromInst(ResNo, Inst.getResult(ResNo), TP);
1695 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; ++i) {
1696 Record *OperandNode = Inst.getOperand(i);
H A DDAGISelMatcherGen.cpp665 GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) { argument
666 const TreePattern *InstPat = Inst.getPattern();
719 const DAGInstruction &Inst = CGP.getInstruction(Op); local
727 const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N);
756 unsigned NumResults = Inst.getNumResults();
H A DInstrInfoEmitter.cpp55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
88 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument
91 for (auto &Op : Inst.Operands) {
180 for (const CodeGenInstruction *Inst : Target.instructions()) {
181 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
208 for (const CodeGenInstruction *Inst : NumberedInstructions) {
209 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
212 for (const auto &Info : Inst->Operands) {
221 OperandMap[OpList].push_back(Namespace + "::" + Inst
362 Record *Inst = II->TheDef; local
461 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument
[all...]
/external/llvm/tools/bugpoint/
H A DCrashDebugger.cpp401 Instruction *Inst = I++; local
402 if (!Instructions.count(Inst) && !isa<TerminatorInst>(Inst) &&
403 !isa<LandingPadInst>(Inst)) {
404 if (!Inst->getType()->isVoidTy())
405 Inst->replaceAllUsesWith(UndefValue::get(Inst->getType()));
406 Inst->eraseFromParent();
/external/llvm/tools/llvm-mc/
H A DDisassembler.cpp66 MCInst Inst; local
69 S = DisAsm.getInstruction(Inst, Size, memoryObject, Index,
92 Streamer.EmitInstruction(Inst, STI);
/external/llvm/tools/llvm-objdump/
H A DMachODump.cpp392 MCInst Inst; local
415 if (DisAsm->getInstruction(Inst, Size, memoryObject, Index,
418 IP->printInst(&Inst, outs(), "");
446 MCInst Inst; local
448 if (DisAsm->getInstruction(Inst, InstSize, memoryObject, Index,
452 IP->printInst(&Inst, outs(), "");
H A Dllvm-objdump.cpp227 IP->printInst(&(*i)->getInsts()->at(ii).Inst, OS, "");
366 IP->printInst(&II->Inst, outs(), "");
513 MCInst Inst; local
515 if (DisAsm->getInstruction(Inst, Size, memoryObject,
523 IP->printInst(&Inst, outs(), "");
/external/llvm/lib/Transforms/Vectorize/
H A DLoopVectorize.cpp497 if (const Instruction *Inst = dyn_cast_or_null<Instruction>(Ptr))
498 B.SetCurrentDebugLocation(Inst->getDebugLoc());
3462 static bool hasOutsideLoopUser(const Loop *TheLoop, Instruction *Inst, argument
3466 if (!Reductions.count(Inst))
3468 for (User *U : Inst->users()) {
5874 bool LoopVectorizationCostModel::isConsecutiveLoadOrStore(Instruction *Inst) {
5876 if (StoreInst *ST = dyn_cast<StoreInst>(Inst))
5880 if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
H A DSLPVectorizer.cpp2432 Instruction *Inst = dyn_cast<Instruction>(VL[i]);
2433 if (!Inst || Inst->getOpcode() != Opcode0)
2973 Value *Inst = BI->getOperand(0); local
2974 if (Inst == P)
2975 Inst = BI->getOperand(1);
2977 if (tryToVectorize(dyn_cast<BinaryOperator>(Inst), R)) {
/external/llvm/bindings/ocaml/llvm/
H A Dllvm_ocaml.c1310 CAMLprim value llvm_instr_get_opcode(LLVMValueRef Inst) {
1312 if (!LLVMIsAInstruction(Inst))
1314 o = LLVMGetInstructionOpcode(Inst);
1335 CAMLprim value llvm_instruction_call_conv(LLVMValueRef Inst) { argument
1336 return Val_int(LLVMGetInstructionCallConv(Inst));
1340 CAMLprim value llvm_set_instruction_call_conv(value CC, LLVMValueRef Inst) { argument
1341 LLVMSetInstructionCallConv(Inst, Int_val(CC));
/external/llvm/include/llvm/Analysis/
H A DMemoryDependenceAnalysis.h104 static MemDepResult getDef(Instruction *Inst) { argument
105 assert(Inst && "Def requires inst");
106 return MemDepResult(PairTy(Inst, Def));
108 static MemDepResult getClobber(Instruction *Inst) { argument
109 assert(Inst && "Clobber requires inst");
110 return MemDepResult(PairTy(Inst, Clobber));
182 static MemDepResult getDirty(Instruction *Inst) { argument
183 return MemDepResult(PairTy(Inst, Invalid));
440 void verifyRemoved(Instruction *Inst) const;
/external/llvm/include/llvm/CodeGen/
H A DMachineModuleInfo.h245 addFrameInst(const MCCFIInstruction &Inst) { argument
246 FrameInstructions.push_back(Inst);
/external/llvm/include/llvm/MC/MCAnalysis/
H A DMCAtom.h115 MCInst Inst; member in class:llvm::MCDecodedInst
118 MCDecodedInst(const MCInst &Inst, uint64_t Address, uint64_t Size) argument
119 : Inst(Inst), Address(Address), Size(Size) {}
133 void addInst(const MCInst &Inst, uint64_t Size);
/external/llvm/include/llvm/MC/
H A DMCAsmInfo.h494 void addInitialFrameState(const MCCFIInstruction &Inst) { argument
495 InitialFrameState.push_back(Inst);
H A DMCAssembler.h293 /// Inst - The instruction this is a fragment for.
294 MCInst Inst; member in class:llvm::MCRelaxableFragment
311 : MCEncodedFragmentWithFixups(FT_Relaxable, SD), Inst(_Inst), STI(_STI) {
317 const MCInst &getInst() const { return Inst; }
318 void setInst(const MCInst& Value) { Inst = Value; }
H A DMCInstBuilder.h23 MCInst Inst; member in class:llvm::MCInstBuilder
28 Inst.setOpcode(Opcode);
33 Inst.addOperand(MCOperand::CreateReg(Reg));
39 Inst.addOperand(MCOperand::CreateImm(Val));
45 Inst.addOperand(MCOperand::CreateFPImm(Val));
51 Inst.addOperand(MCOperand::CreateExpr(Val));
57 Inst.addOperand(MCOperand::CreateInst(Val));
62 return Inst;
H A DMCTargetAsmParser.h178 virtual unsigned checkTargetMatchPredicate(MCInst &Inst) { argument

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