/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 317 MachineRegisterInfo &MRI = MF.getRegInfo(); local 319 if (!MRI.isLiveIn(Reg)) { 320 VirtualRegister = MRI.createVirtualRegister(RC); 321 MRI.addLiveIn(Reg, VirtualRegister); 323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
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H A D | AMDGPUInstrInfo.cpp | 241 MachineRegisterInfo &MRI = MF.getRegInfo(); local 249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); 254 MRI.setRegClass(MO.getReg(), newRegClass);
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H A D | R600ISelLowering.cpp | 57 MachineRegisterInfo &MRI = MF->getRegInfo(); local 111 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister); 120 unsigned NewAddr = MRI.createVirtualRegister( 122 unsigned ShiftValue = MRI.createVirtualRegister( 157 unsigned t0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 158 unsigned t1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass); 179 unsigned t0 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass); 180 unsigned t1 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass); 260 MachineRegisterInfo &MRI = MF.getRegInfo(); local 263 if (!MRI [all...] |
H A D | SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI, 90 MachineRegisterInfo &MRI = MF.getRegInfo(); local 97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]); 113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); 114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg); 115 AddLiveIn(&MF, MRI, new_reg, virt_reg); 123 MachineRegisterInfo & MRI, 127 if (!MRI.isLiveIn(physReg)) { 128 MRI.addLiveIn(physReg, virtReg); 134 MRI 122 AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI, unsigned physReg, unsigned virtReg) argument [all...] |
H A D | SIISelLowering.cpp | 69 MachineRegisterInfo & MRI = BB->getParent()->getRegInfo(); local 127 LowerSI_INTERP(MI, *BB, I, MRI); 130 LowerSI_INTERP_CONST(MI, *BB, I, MRI); 133 LowerSI_KIL(MI, *BB, I, MRI); 136 LowerSI_V_CNDLT(MI, *BB, I, MRI); 150 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const 152 unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); 153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); 183 MachineRegisterInfo &MRI) const 189 unsigned M0 = MRI [all...] |
/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.h | 14 const MCRegisterInfo &MRI) 15 : MCInstPrinter(MAI, MII, MRI) {} 13 AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.cpp | 68 const MCRegisterInfo &MRI, 70 return new AMDGPUInstPrinter(MAI, MII, MRI); 64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 53 MachineRegisterInfo &MRI; member in class:llvm::FastISel
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H A D | LiveIntervalAnalysis.h | 52 MachineRegisterInfo* MRI; member in class:llvm::LiveIntervals
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H A D | LiveRangeEdit.h | 62 MachineRegisterInfo &MRI; member in class:llvm::LiveRangeEdit 121 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm), 125 ScannedRemattable(false) { MRI.setDelegate(this); } 127 ~LiveRangeEdit() { MRI.resetDelegate(this); }
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H A D | LiveRegMatrix.h | 41 MachineRegisterInfo *MRI; member in class:llvm::LiveRegMatrix
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H A D | LiveVariables.h | 111 MachineRegisterInfo &MRI); 130 MachineRegisterInfo* MRI; member in class:llvm::LiveVariables 282 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
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H A D | MachineRegisterInfo.h | 977 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { argument 978 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); 980 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
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H A D | MachineSSAUpdater.h | 55 MachineRegisterInfo *MRI; member in class:llvm::MachineSSAUpdater
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H A D | MachineTraceMetrics.h | 71 const MachineRegisterInfo *MRI; member in class:llvm::MachineTraceMetrics
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H A D | RegisterScavenging.h | 34 MachineRegisterInfo* MRI; member in class:llvm::RegScavenger 165 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
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H A D | ScheduleDAG.h | 558 MachineRegisterInfo &MRI; // Virtual/real register map member in class:llvm::SUnit::ScheduleDAG
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H A D | VirtRegMap.h | 41 MachineRegisterInfo *MRI; member in class:llvm::VirtRegMap 85 MachineRegisterInfo &getRegInfo() const { return *MRI; }
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/external/llvm/include/llvm/MC/ |
H A D | MCContext.h | 62 const MCRegisterInfo *MRI; member in class:llvm::MCContext 179 explicit MCContext(const MCAsmInfo *MAI, const MCRegisterInfo *MRI, 188 const MCRegisterInfo *getRegisterInfo() const { return MRI; }
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H A D | MCInstPrinter.h | 41 const MCRegisterInfo &MRI; member in class:llvm::MCInstPrinter 60 : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri),
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/external/llvm/include/llvm/Support/ |
H A D | TargetRegistry.h | 82 typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI, 105 const MCRegisterInfo &MRI, 120 const MCRegisterInfo &MRI, 123 const MCRegisterInfo &MRI, 283 MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, argument 287 return MCAsmInfoCtorFn(MRI, Triple); 361 MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, argument 365 return MCAsmBackendCtorFn(*this, MRI, Triple, CPU); 400 const MCRegisterInfo &MRI, 404 return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, MII, MRI, ST 397 createMCInstPrinter(unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) const argument 409 createMCCodeEmitter(const MCInstrInfo &II, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) const argument 1088 Allocator(const Target &T, const MCRegisterInfo &MRI, StringRef Triple, StringRef CPU) argument [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 271 const MachineRegisterInfo *MRI = nullptr) const; 793 const MachineRegisterInfo *MRI) const { 805 const MachineRegisterInfo *MRI, 813 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 818 unsigned Reg, MachineRegisterInfo *MRI) const { 891 const MachineRegisterInfo *MRI, 804 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const argument 890 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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/external/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.h | 119 MachineRegisterInfo &MRI; member in class:llvm::AggressiveAntiDepBreaker
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H A D | BranchFolding.cpp | 196 MachineRegisterInfo &MRI = MF.getRegInfo(); local 197 if (MRI.tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF)) 200 MRI.invalidateLiveness();
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H A D | CalcSpillWeights.cpp | 33 MachineRegisterInfo &MRI = MF.getRegInfo(); local 35 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) { 37 if (MRI.reg_nodbg_empty(Reg))
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