/external/webrtc/src/modules/audio_coding/codecs/isac/main/source/ |
H A D | entropy_coding.c | 523 /* Find RC coefficients. */ 526 /* Quantize & code RC Coefficient. */ 529 /* RC -> AR coefficients */ 595 void WebRtcIsac_Rc2Poly(double* RC, int N, double* a) { argument 604 a[m] = RC[m - 1]; 606 a[k] += RC[m - 1] * tmp[m - k]; 613 void WebRtcIsac_Poly2Rc(double* a, int N, double* RC) { argument 618 RC[N - 1] = a[N]; 620 tmp_inv = 1.0 / (1.0 - RC[m] * RC[ [all...] |
/external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/ |
H A D | SkPdfAppearanceCharacteristicsDictionary_autogen.cpp | 59 SkString SkPdfAppearanceCharacteristicsDictionary::RC(SkPdfNativeDoc* doc) { function in class:SkPdfAppearanceCharacteristicsDictionary 60 SkPdfNativeObject* ret = get("RC", ""); 68 return get("RC", "") != NULL;
|
/external/owasp/sanitizer/tools/findbugs/lib/ |
H A D | bcel.jar | META-INF/ META-INF/MANIFEST.MF org/ org/apache/ org/apache/bcel/ org/apache/bcel/classfile/ ... |
/external/pcre/dist/sljit/ |
H A D | sljitNativePPC_common.c | 128 #define RC(flags) ((flags & ALT_SET_FLAGS) >> 10) macro 535 /* This flag affects the RC() and OERC() macros. */
|
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 314 const TargetRegisterClass *RC, 320 VirtualRegister = MRI.createVirtualRegister(RC); 313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
|
H A D | AMDGPUInstrInfo.cpp | 126 const TargetRegisterClass *RC, 135 const TargetRegisterClass *RC, 233 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
/external/llvm/utils/TableGen/ |
H A D | AsmMatcherEmitter.cpp | 1171 const CodeGenRegisterClass &RC = **it; local 1173 Record *Def = RC.getDef(); 1176 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), 1177 RC.getOrder().end())]; 1179 CI->ClassName = RC.getName(); 1180 CI->Name = "MCK_" + RC.getName(); 1181 CI->ValueName = RC.getName(); 1183 CI->ValueName = CI->ValueName + "," + RC.getName();
|
H A D | CodeGenRegisters.cpp | 789 // Returns true if RC is a strict subclass. 790 // RC is a sub-class of this class if it is a valid replacement for any 794 // 1. All RC registers are also in this. 795 // 2. The RC spill size must not be smaller than our spill size. 796 // 3. RC spill alignment must be compatible with ours. 857 CodeGenRegisterClass &RC = *RegClasses[rci - 1]; local 858 RC.SubClasses.resize(RegClasses.size()); 859 RC.SubClasses.set(RC.EnumValue); 861 // Normally, all subclasses have IDs >= rci, unless RC i 1040 addToMaps(CodeGenRegisterClass *RC) argument 1054 getOrCreateSubClass(const CodeGenRegisterClass *RC, const CodeGenRegister::Set *Members, StringRef Name) argument 1742 inferCommonSubClass(CodeGenRegisterClass *RC) argument 1780 inferSubClassWithSubReg(CodeGenRegisterClass *RC) argument 1823 inferMatchingSuperRegClass(CodeGenRegisterClass *RC, unsigned FirstSubRegRC) argument 1891 CodeGenRegisterClass *RC = RegClasses[rci]; local 1928 const CodeGenRegisterClass &RC = *RCs[i]; local [all...] |
H A D | CodeGenRegisters.h | 265 // R:SubRegIndex in this RC for all R in SuperRC. 302 // Returns true if RC is a subclass. 303 // RC is a sub-class of this class if it is a valid replacement for any 307 // 1. All RC registers are also in this. 308 // 2. The RC spill size must not be smaller than our spill size. 309 // 3. RC spill alignment must be compatible with ours. 311 bool hasSubClass(const CodeGenRegisterClass *RC) const { 312 return SubClasses.test(RC->EnumValue); 381 Key(const CodeGenRegisterClass &RC) argument 382 : Members(&RC [all...] |
H A D | CodeGenTarget.cpp | 239 const CodeGenRegisterClass &RC = *RCs[i]; local 240 if (RC.contains(Reg)) { 241 ArrayRef<MVT::SimpleValueType> InVTs = RC.getValueTypes(); 430 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, argument 432 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
|
H A D | DAGISelMatcherGen.cpp | 33 const CodeGenRegisterClass &RC = *RCs[rc]; local 34 if (!RC.contains(Reg)) 39 VT = RC.getValueTypeNum(0); 44 assert(VT == RC.getValueTypeNum(0));
|
H A D | FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC; member in struct:__anon26590::InstructionMemo 255 const CodeGenRegisterClass *RC = nullptr; 259 RC = &Target.getRegisterClass(OpLeafRec); 261 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 263 RC = OrigDstRC; 268 if (!RC) 274 if (DstRC != RC && !DstRC->hasSubClass(RC)) 277 DstRC = RC; 651 OS << "&" << InstNS << Memo.RC [all...] |
H A D | RegisterInfoEmitter.cpp | 167 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 170 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; local 171 const CodeGenRegister::Set &Regs = RC.getMembers(); 176 RC.buildRegUnitSet(RegUnits); 180 OS << "}, \t// " << RC.getName() << "\n"; 183 << " return RCWeightTable[RC->getID()];\n" 285 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 291 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n" 853 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 854 ArrayRef<Record*> Order = RC 887 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 995 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local 1033 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 1098 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 1127 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 1143 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local 1179 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local 1245 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 562 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 565 /// register to be a common subclass of RC and the current register class, 572 const TargetRegisterClass *RC, 980 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); local 981 PSet = TRI->getRegClassPressureSets(RC); 982 Weight = TRI->getRegClassWeight(RC).RegWeight;
|
H A D | RegisterClassInfo.h | 66 // Compute all information about RC. 67 void compute(const TargetRegisterClass *RC) const; 69 // Return an up-to-date RCInfo for RC. 70 const RCInfo &get(const TargetRegisterClass *RC) const { 71 const RCInfo &RCI = RegClass[RC->getID()]; 73 compute(RC); 85 /// registers in RC in the current function. 86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { 87 return get(RC).NumRegs; 90 /// getOrder - Returns the preferred allocation order for RC 119 getMinCost(const TargetRegisterClass *RC) argument 127 getLastCostChange(const TargetRegisterClass *RC) argument [all...] |
/external/llvm/include/llvm/IR/ |
H A D | InlineAsm.h | 251 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) { argument 252 // Store RC + 1, reserve the value 0 to mean 'no register class'. 253 ++RC; 254 assert(RC <= 0x7fff && "Too large register class ID"); 256 return InputFlag | (RC << 16); 289 /// class constraint. Sets RC to the register class ID. 290 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) { argument 295 // stores RC + 1. 298 RC = High - 1;
|
/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 199 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 529 const TargetRegisterClass *RC, 542 const TargetRegisterClass *RC, 736 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 526 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 539 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
H A D | TargetLowering.h | 315 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; local 316 assert(RC && "This value type is not natively supported!"); 317 return RC; 328 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; local 329 return RC; 1074 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { argument 1076 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 1077 RegClassForVT[VT.SimpleTy] = RC; 1847 bool isLegalRC(const TargetRegisterClass *RC) const;
|
/external/llvm/lib/Analysis/ |
H A D | ScalarEvolution.cpp | 538 const SCEVConstant *RC = cast<SCEVConstant>(RHS); local 542 const APInt &RA = RC->getValue()->getValue(); 582 const SCEVNAryExpr *RC = cast<SCEVNAryExpr>(RHS); local 585 unsigned LNumOps = LC->getNumOperands(), RNumOps = RC->getNumOperands(); 592 long X = compare(LC->getOperand(i), RC->getOperand(i)); 601 const SCEVUDivExpr *RC = cast<SCEVUDivExpr>(RHS); local 604 long X = compare(LC->getLHS(), RC->getLHS()); 607 return compare(LC->getRHS(), RC->getRHS()); 614 const SCEVCastExpr *RC = cast<SCEVCastExpr>(RHS); local 617 return compare(LC->getOperand(), RC [all...] |
/external/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.h | 44 /// RC - The register class 45 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon25719
|
H A D | CriticalAntiDepBreaker.cpp | 403 const TargetRegisterClass *RC, 406 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); 637 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] local 639 assert((AntiDepReg == 0 || RC != nullptr) && 641 if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 655 RC, ForbidRegs)) { 399 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC, SmallVectorImpl<unsigned> &Forbid) argument
|
H A D | ExecutionDepsFix.cpp | 131 const TargetRegisterClass *const RC; member in class:__anon25744::ExeDepsFix 157 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} 521 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr 719 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); 722 << RC->getName() << " **********\n"); 727 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end(); 737 // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC, 740 for (unsigned i = 0, e = RC 795 createExecutionDependencyFixPass(const TargetRegisterClass *RC) argument [all...] |
H A D | LiveStackAnalysis.cpp | 59 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 65 S2RCMap.insert(std::make_pair(Slot, RC)); 69 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 81 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 82 if (RC) 83 OS << " [" << RC->getName() << "]\n";
|
H A D | LocalStackSlotAllocation.cpp | 391 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); local 392 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
|
H A D | MachineBasicBlock.cpp | 352 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { argument 355 assert(RC && "Register class is required"); 369 if (!MRI.constrainRegClass(VirtReg, RC)) 375 unsigned VirtReg = MRI.createVirtualRegister(RC);
|