Searched defs:STI (Results 1 - 25 of 104) sorted by last modified time

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/external/mesa3d/src/mesa/x86/
H A Dassyntax.h663 #define STI CHOICE(sti, sti, sti) macro
1384 #define STI sti macro
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_debug.cpp217 const MCSubtargetInfo *STI = T->createMCSubtargetInfo(Triple, sys::getHostCPUName(), ""); local
218 OwningPtr<const MCDisassembler> DisAsm(T->createMCDisassembler(*STI));
251 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
254 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *STI));
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUMCTargetDesc.cpp69 const MCSubtargetInfo &STI) {
74 const MCSubtargetInfo &STI,
76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
77 return createSIMCCodeEmitter(MCII, STI, Ctx);
79 return createR600MCCodeEmitter(MCII, STI, Ctx);
64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
73 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
H A DR600MCCodeEmitter.cpp43 const MCSubtargetInfo &STI; member in class:__anon27321::R600MCCodeEmitter
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
145 const MCSubtargetInfo &STI,
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
144 createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
H A DSIMCCodeEmitter.cpp63 const MCSubtargetInfo &STI; member in class:__anon27323::SIMCCodeEmitter
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
126 const MCSubtargetInfo &STI,
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
125 createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/llvm/tools/llvm-mc/
H A DDisassembler.cpp57 const MCSubtargetInfo &STI) {
92 Streamer.EmitInstruction(Inst, STI);
159 MCSubtargetInfo &STI,
181 T.createMCDisassembler(STI, Ctx));
225 InAtomicBlock, STI);
53 PrintInsts(const MCDisassembler &DisAsm, const ByteArrayTy &Bytes, SourceMgr &SM, raw_ostream &Out, MCStreamer &Streamer, bool InAtomicBlock, const MCSubtargetInfo &STI) argument
157 disassemble(const Target &T, const std::string &Triple, MCSubtargetInfo &STI, MCStreamer &Streamer, MemoryBuffer &Buffer, SourceMgr &SM, raw_ostream &Out) argument
H A Dllvm-mc.cpp322 MCAsmInfo &MAI, MCSubtargetInfo &STI,
327 TheTarget->createMCAsmParser(STI, *Parser, MCII, MCOptions));
446 std::unique_ptr<MCSubtargetInfo> STI(
452 TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI, *STI);
461 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
472 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
475 FOS, CE, *STI, RelaxAll,
486 Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI,
499 Res = Disassembler::disassemble(*TheTarget, TripleName, *STI, *Str,
320 AssembleInput(const char *ProgName, const Target *TheTarget, SourceMgr &SrcMgr, MCContext &Ctx, MCStreamer &Str, MCAsmInfo &MAI, MCSubtargetInfo &STI, MCInstrInfo &MCII, MCTargetOptions &MCOptions) argument
/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h37 const TargetSubtargetInfo *STI; member in class:llvm::TargetSchedModel
44 TargetSchedModel(): STI(nullptr), TII(nullptr) {}
115 return STI->getWriteProcResBegin(SC);
118 return STI->getWriteProcResEnd(SC);
/external/llvm/include/llvm/MC/
H A DMCAssembler.h296 /// STI - The MCSubtargetInfo in effect when the instruction was encoded.
297 /// Keep a copy instead of a reference to make sure that updates to STI
299 const MCSubtargetInfo STI; member in class:llvm::MCRelaxableFragment
311 : MCEncodedFragmentWithFixups(FT_Relaxable, SD), Inst(_Inst), STI(_STI) {
320 const MCSubtargetInfo &getSubtargetInfo() { return STI; }
H A DMCDisassembler.h58 MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) argument
59 : Ctx(Ctx), STI(STI), Symbolizer(), CommentStream(nullptr) {}
90 const MCSubtargetInfo &STI; member in class:llvm::MCDisassembler
108 const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
H A DMCInstrDesc.h168 bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI, argument
171 return ComplexDeprecationInfo(MI, STI, Info);
172 if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
/external/llvm/include/llvm/Support/
H A DTargetRegistry.h109 MCSubtargetInfo &STI,
114 const MCSubtargetInfo &STI,
121 const MCSubtargetInfo &STI);
124 const MCSubtargetInfo &STI,
132 const MCSubtargetInfo &STI,
373 MCSubtargetInfo &STI,
379 return MCAsmParserCtorFn(STI, Parser, MII, Options);
390 MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI, argument
394 return MCDisassemblerCtorFn(*this, STI, Ctx);
401 const MCSubtargetInfo &STI) cons
372 createMCAsmParser( MCSubtargetInfo &STI, MCAsmParser &Parser, const MCInstrInfo &MII, const MCTargetOptions &Options) const argument
409 createMCCodeEmitter(const MCInstrInfo &II, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) const argument
427 createMCObjectStreamer(StringRef TT, MCContext &Ctx, MCAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) const argument
1110 Allocator(MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII, const MCTargetOptions &Options) argument
[all...]
/external/llvm/lib/CodeGen/
H A DLLVMTargetMachine.cpp171 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
178 MII, MRI, STI);
183 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
197 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
205 getTargetTriple(), *Context, *MAB, Out, MCE, STI, local
269 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); local
271 STI, *Ctx);
279 getTargetTriple(), *Ctx, *MAB, Out, MCE, STI, local
H A DTargetInstrInfo.cpp674 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, argument
/external/llvm/lib/MC/
H A DMCAsmStreamer.cpp230 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
1174 const MCSubtargetInfo &STI) {
1179 Emitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
1258 void MCAsmStreamer::EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) {
1264 AddEncodingComment(Inst, STI);
1173 AddEncodingComment(const MCInst &Inst, const MCSubtargetInfo &STI) argument
H A DMCELFStreamer.cpp397 const MCSubtargetInfo &STI) {
398 this->MCObjectStreamer::EmitInstToFragment(Inst, STI);
406 const MCSubtargetInfo &STI) {
411 Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
396 EmitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &STI) argument
405 EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) argument
H A DMCMachOStreamer.cpp47 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) override;
399 const MCSubtargetInfo &STI) {
405 getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
398 EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) argument
H A DMCObjectStreamer.cpp188 const MCSubtargetInfo &STI) {
189 MCStreamer::EmitInstruction(Inst, STI);
201 EmitInstToData(Inst, STI);
216 EmitInstToData(Relaxed, STI);
221 EmitInstToFragment(Inst, STI);
225 const MCSubtargetInfo &STI) {
228 MCRelaxableFragment *IF = new MCRelaxableFragment(Inst, STI);
234 STI);
187 EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) argument
224 EmitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &STI) argument
H A DMCStreamer.cpp650 const MCSubtargetInfo &STI) {
649 EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) argument
H A DWinCOFFStreamer.cpp46 const MCSubtargetInfo &STI) {
52 getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
45 EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) argument
/external/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp62 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU, local
64 if (!STI)
73 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx);
89 *MAI, *MII, *MRI, *STI);
96 STI, MII, Ctx, DisAsm, IP);
185 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); local
186 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
204 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); local
205 const MCSchedModel *SCModel = STI->getSchedModel();
228 const MCWriteLatencyEntry *WLEntry = STI
334 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); local
[all...]
/external/llvm/lib/Object/
H A DRecordStreamer.cpp71 const MCSubtargetInfo &STI) {
72 MCStreamer::EmitInstruction(Inst, STI);
70 EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp31 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI) argument
33 RI(this, &STI), Subtarget(STI) {}
H A DAArch64RegisterInfo.h31 const AArch64Subtarget *STI; member in struct:llvm::AArch64RegisterInfo
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp43 MCSubtargetInfo &STI; member in class:__anon25951::AArch64AsmParser
119 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
125 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
2652 STI.getFeatureBits(), getContext()));
3821 Out.EmitInstruction(Inst, STI);
3981 getParser().getStreamer().EmitInstruction(Inst, STI);

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