Searched defs:Shift (Results 1 - 25 of 59) sorted by last modified time

123

/external/vixl/src/a64/
H A Dconstants-a64.h222 enum Shift { enum in namespace:vixl
/external/valgrind/main/VEX/priv/
H A Dhost_arm64_defs.h662 } Shift; member in union:__anon31763::__anon31764
H A Dhost_arm_defs.h641 } Shift; member in union:__anon31854::__anon31855
/external/qemu/distrib/sdl-1.2.15/src/main/symbian/EKA2/
H A DSDL_main.cpp82 const TWsEvent& Shift();
130 const TWsEvent& CEventQueue::Shift() function in class:CEventQueue
132 const TWsEvent& event = iVector.Shift();
H A Dvectorbuffer.h50 TPtrC8 Shift();
143 //Shift(); //data is lost
149 TPtrC8 TVectorBuffer<C>::Shift() function in class:TVectorBuffer
163 return Shift(); //this happens when buffer is terminated, and data lies in next
200 const T& Shift();
218 const T& TVector<T, C>::Shift() function in class:TVector
220 const TPtrC8 ptr = TVectorBuffer<C * sizeof(T)>::Shift();
/external/pdfium/core/src/fxcodec/lcms2/lcms2-2.6/src/
H A Dcmshalf.c462 static cmsUInt8Number Shift[512] = { variable
531 return (cmsUInt16Number) ((cmsUInt32Number) Base[ j ] + (( n & 0x007fffff) >> Shift[ j ]));
/external/pdfium/fpdfsdk/src/javascript/
H A DJS_EventHandler.cpp592 FX_BOOL CJS_EventHandler::Shift() function in class:CJS_EventHandler
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp438 SDValue Shift = DAG.getConstant(shiftBits, DVT); local
439 // Shift left by 'Shift' bits.
440 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift);
441 // Signed shift Right by 'Shift' bits.
442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
/external/lzma/C/
H A DPpmd.h36 Byte Shift; /* Speed of Freq change; low Shift is for fast change */ member in struct:__anon26720
37 Byte Count; /* Count to next change of Shift */
40 #define Ppmd_See_Update(p) if ((p)->Shift < PPMD_PERIOD_BITS && --(p)->Count == 0) \
41 { (p)->Summ <<= 1; (p)->Count = (Byte)(3 << (p)->Shift++); }
/external/llvm/include/llvm/Support/
H A DLEB128.h83 unsigned Shift = 0; local
85 Value += (*p & 0x7f) << Shift;
86 Shift += 7;
H A DMathExtras.h59 T Shift = std::numeric_limits<T>::digits >> 1; local
60 T Mask = std::numeric_limits<T>::max() >> Shift;
61 while (Shift) {
63 Val >>= Shift; local
64 ZeroBits |= Shift;
66 Shift >>= 1;
67 Mask >>= Shift; local
128 for (T Shift = std::numeric_limits<T>::digits >> 1; Shift; Shift >>
[all...]
H A DScaledNumber.h89 // Shift right and round.
90 int Shift = 64 - Width - countLeadingZeros(Digits); local
91 return getRounded<DigitsT>(Digits >> Shift, Scale + Shift,
92 Digits & (UINT64_C(1) << (Shift - 1)));
278 /// scales in place. Shift the digits as necessary to form equivalent numbers,
308 // Shift LDigits left as much as possible, then shift RDigits right.
625 ScaledNumber &operator<<=(int16_t Shift) { argument
626 shiftLeft(Shift);
629 ScaledNumber &operator>>=(int16_t Shift) { argument
709 adjustToWidth(uint64_t N, int32_t Shift) argument
832 shiftLeft(int32_t Shift) argument
859 Digits <<= Shift; local
863 shiftRight(int32_t Shift) argument
886 Digits >>= Shift; local
[all...]
/external/llvm/lib/Analysis/
H A DBlockFrequencyInfoImpl.cpp189 static uint64_t shiftRightAndRound(uint64_t N, int Shift) {
190 assert(Shift >= 0);
191 assert(Shift < 64);
192 if (!Shift)
194 return (N >> Shift) + (UINT64_C(1) & N >> (Shift - 1));
216 int Shift = 0; local
218 Shift = 33;
220 Shift = 33 - countLeadingZeros(Total);
223 if (!Shift)
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp370 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
3442 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { argument
3453 Shift = Op;
4079 SDValue Shift; local
4082 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4086 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4089 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
4199 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT, local
4202 Shift);
4689 SDValue Shift local
8088 unsigned Shift; member in struct:__anon25800::LoadedSlice::Cost
8165 unsigned Shift; member in struct:__anon25800::LoadedSlice
8193 UsedBits <<= Shift; local
8539 unsigned Shift = 0; local
11218 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), local
11230 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), local
11382 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType, local
[all...]
H A DSelectionDAG.cpp3187 "Shift operators return type must be the same as their first arg");
3336 unsigned Shift = ElementSize * N2C->getZExtValue(); local
3337 APInt ShiftedVal = C->getAPIntValue().lshr(Shift);
H A DSelectionDAGISel.cpp1897 unsigned Shift = 7; local
1901 Val |= (NextBits&127) << Shift;
1902 Shift += 7;
H A DTargetLowering.cpp983 SDValue Shift = In.getOperand(1); local
986 Shift =
1003 Shift));
1676 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), local
1679 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1704 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, local
1707 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2623 // Shift the value upfront if it is even, so the LSB is one.
2685 // Shift right algebraic if shift value is nonzero
2725 unsigned Shift local
2854 SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT)); local
[all...]
/external/llvm/lib/Support/
H A DScaledNumber.cpp46 // Shift as little as possible to maximize precision.
48 int Shift = 64 - LeadingZeros; local
50 Upper = Upper << LeadingZeros | Lower >> Shift;
51 return getRounded(Upper, Shift,
52 Shift && (Lower & UINT64_C(1) << (Shift - 1)));
64 int Shift = 0; local
66 Shift -= Zeros;
74 return getAdjusted<uint32_t>(Quotient, Shift);
77 return getRounded<uint32_t>(Quotient, Shift, Remainde
86 int Shift = 0; local
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp75 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
76 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
77 bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
78 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) { argument
79 return SelectShiftedRegister(N, false, Reg, Shift);
81 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) { argument
82 return SelectShiftedRegister(N, true, Reg, Shift);
166 SDValue &Shift);
227 /// Val set to the 12-bit value and Shift set to the shifter operand.
229 SDValue &Shift) {
228 SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift) argument
257 SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift) argument
318 SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg, SDValue &Shift) argument
535 SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift) argument
[all...]
H A DAArch64ISelLowering.cpp5040 SDValue Shift = N->getOperand(1);
5043 unsigned ShiftOpc = Shift.getOpcode();
5049 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5069 SDValue Y = Shift.getOperand(0);
5075 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
6319 unsigned Shift = (63 - LZ) / 16; local
6321 return (Shift < 3) ? true : false;
6722 SDValue Shift = N->getOperand(2); local
6742 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp662 unsigned Shift = ShiftedImm.ShiftAmount; local
664 if (Shift != 0 && Shift != 12)
813 template<int RegWidth, int Shift>
825 if (Value == 0 && Shift != 0)
828 return (Value & ~(0xffffULL << Shift)) == 0;
831 template<int RegWidth, int Shift>
848 return (Value & ~(0xffffULL << Shift)) == 0;
1045 unsigned Shift = getShiftExtendAmount(); local
1047 (Shift
1055 unsigned Shift = getShiftExtendAmount(); local
1065 unsigned Shift = getShiftExtendAmount(); local
1730 unsigned Shift = getShiftedImmShift(); local
[all...]
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp945 unsigned Shift = local
948 if (Shift != 0)
952 *CommentStream << '=' << (Val << Shift) << '\n';
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp2622 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi. member in struct:InstructionTable
2626 { // ARM Opc S Shift Imm
2634 { // Thumb Opc S Shift Imm
2644 { // ARM Opc S Shift Imm
2652 { // Thumb Opc S Shift Imm
2682 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; local
2683 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2694 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2709 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
[all...]
H A DARMISelDAGToDAG.cpp94 bool isShifterOpProfitable(const SDValue &Shift,
455 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift, argument
460 if (Shift.hasOneUse())
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp408 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; local
409 EmitByte((Val >> Shift) & 0xff, OS);
1118 Binary <<= 7; // Shift amount is bits [11:7]
1119 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]

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