Searched defs:cond (Results 1 - 25 of 285) sorted by last modified time

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/external/webrtc/src/system_wrappers/source/
H A Devent_posix.h52 pthread_cond_t cond; member in class:webrtc::EventPosix
/external/vixl/src/a64/
H A Dassembler-a64.cc454 void Assembler::b(int imm19, Condition cond) { argument
455 Emit(B_cond | ImmCondBranch(imm19) | cond);
464 void Assembler::b(Label* label, Condition cond) { argument
465 b(UpdateAndGetInstructionOffsetTo(label), cond); local
784 Condition cond) {
785 ConditionalSelect(rd, rn, rm, cond, CSEL);
792 Condition cond) {
793 ConditionalSelect(rd, rn, rm, cond, CSINC);
800 Condition cond) {
801 ConditionalSelect(rd, rn, rm, cond, CSIN
781 csel(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
789 csinc(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
797 csinv(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
805 csneg(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
813 cset(const Register &rd, Condition cond) argument
820 csetm(const Register &rd, Condition cond) argument
827 cinc(const Register &rd, const Register &rn, Condition cond) argument
833 cinv(const Register &rd, const Register &rn, Condition cond) argument
839 cneg(const Register &rd, const Register &rn, Condition cond) argument
845 ConditionalSelect(const Register& rd, const Register& rn, const Register& rm, Condition cond, ConditionalSelectOp op) argument
856 ccmn(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
864 ccmp(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
1406 fccmp(const FPRegister& fn, const FPRegister& fm, StatusFlags nzcv, Condition cond) argument
1415 fcsel(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm, Condition cond) argument
1694 ConditionalCompare(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond, ConditionalCompareOp op) argument
[all...]
H A Dconstants-a64.h183 inline Condition InvertCondition(Condition cond) { argument
186 VIXL_ASSERT((cond != al) && (cond != nv));
187 return static_cast<Condition>(cond ^ 1);
H A Ddisasm-a64.cc385 Condition cond = static_cast<Condition>(instr->Condition()); local
386 bool invertible_cond = (cond != al) && (cond != nv);
1551 int cond; local
1553 case 'B': cond = instr->ConditionBranch(); break;
1555 cond = InvertCondition(static_cast<Condition>(instr->Condition()));
1558 default: cond = instr->Condition();
1560 AppendToOutput("%s", condition_code[cond]);
H A Dmacro-assembler-a64.cc389 Condition cond) {
392 ConditionalCompareMacro(rn, -operand.immediate(), nzcv, cond, CCMN);
394 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP);
402 Condition cond) {
405 ConditionalCompareMacro(rn, -operand.immediate(), nzcv, cond, CCMP);
407 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN);
415 Condition cond,
417 VIXL_ASSERT((cond != al) && (cond != nv));
422 ConditionalCompare(rn, operand, nzcv, cond, o
386 Ccmp(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
399 Ccmn(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond) argument
412 ConditionalCompareMacro(const Register& rn, const Operand& operand, StatusFlags nzcv, Condition cond, ConditionalCompareOp op) argument
434 Csel(const Register& rd, const Register& rn, const Operand& operand, Condition cond) argument
[all...]
H A Dmacro-assembler-a64.h195 Condition cond);
199 Condition cond);
203 Condition cond,
208 Condition cond);
381 void B(Label* label, Condition cond) { argument
383 VIXL_ASSERT((cond != al) && (cond != nv));
384 b(label, cond);
386 void B(Condition cond, Label* label) { argument
387 B(label, cond);
439 Cinc(const Register& rd, const Register& rn, Condition cond) argument
445 Cinv(const Register& rd, const Register& rn, Condition cond) argument
463 Cneg(const Register& rd, const Register& rn, Condition cond) argument
469 Cset(const Register& rd, Condition cond) argument
474 Csetm(const Register& rd, Condition cond) argument
479 Csinc(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
490 Csinv(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
501 Csneg(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument
538 Fccmp(const FPRegister& fn, const FPRegister& fm, StatusFlags nzcv, Condition cond) argument
551 Fcsel(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm, Condition cond) argument
[all...]
/external/valgrind/main/VEX/priv/
H A Dguest_amd64_helpers.c814 ULong amd64g_calculate_condition ( ULong/*AMD64Condcode*/ cond, argument
823 ULong inv = cond & 1;
827 tab_cond[cc_op][cond]++;
832 switch (cond) {
885 cond, cc_op, cc_dep1, cc_dep2, cc_ndep );
979 IRExpr *cond, *cc_op, *cc_dep1, *cc_dep2; local
981 cond = args[0];
988 if (isU64(cc_op, AMD64G_CC_OP_ADDQ) && isU64(cond, AMD64CondZ)) {
998 if (isU64(cc_op, AMD64G_CC_OP_SUBQ) && isU64(cond, AMD64CondZ)) {
1003 if (isU64(cc_op, AMD64G_CC_OP_SUBQ) && isU64(cond, AMD64CondN
[all...]
H A Dguest_amd64_toIR.c1660 static IRExpr* mk_amd64g_calculate_condition ( AMD64Condcode cond )
1663 = mkIRExprVec_5( mkU64(cond),
1931 static const HChar* name_AMD64Condcode ( AMD64Condcode cond )
1933 switch (cond) {
1956 AMD64Condcode positiveIse_AMD64Condcode ( AMD64Condcode cond, argument
1959 vassert(cond >= AMD64CondO && cond <= AMD64CondNLE);
1960 if (cond & 1) {
1962 return cond-1;
1965 return cond;
2244 jcc_01( DisResult* dres, AMD64Condcode cond, Addr64 d64_false, Addr64 d64_true ) argument
4611 dis_REP_op( DisResult* dres, AMD64Condcode cond, void (*dis_OP)(Int, IRTemp, Prefix), Int sz, Addr64 rip, Addr64 rip_next, const HChar* name, Prefix pfx ) argument
5082 maybe_put_ST( IRTemp cond, Int i, IRExpr* value ) argument
8333 IRTemp cond = newTemp(Ity_I1); local
8443 dis_cmov_E_G( VexAbiInfo* vbi, Prefix pfx, Int sz, AMD64Condcode cond, Long delta0 ) argument
20627 IRExpr* cond = NULL; local
27210 IRTemp res[8], cond; local
27275 IRTemp cond; local
29209 IRTemp cond = newTemp(Ity_I1); local
[all...]
H A Dguest_arm64_helpers.c103 tab_eval[(UInt)(_cc_op)][(UInt)(cond)]++; \
614 ULong cond = cond_n_op >> 4; local
616 ULong inv = cond & 1;
620 NOTE_EVAL(cc_op, cond);
626 switch (cond) {
674 cond, cc_op, cc_dep1, cc_dep2, cc_dep3 );
H A Dguest_arm64_toIR.c1232 static const HChar* nameARM64Condcode ( ARM64Condcode cond )
1234 switch (cond) {
1256 static const HChar* nameCC ( ARM64Condcode cond ) {
1257 return nameARM64Condcode(cond);
1264 Ity_I64, the returned value is either 0 or 1. 'cond' must be
1268 static IRExpr* mk_arm64g_calculate_condition_dyn ( IRExpr* cond )
1270 vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I64);
1271 /* And 'cond' had better produce a value in which only bits 7:4 are
1275 "(cond << 4) | stored-operation".
1276 However, as per comments above, 'cond' mus
1462 setFlags_ADD_SUB_conditionally( Bool is64, Bool isSUB, IRTemp cond, IRTemp argL, IRTemp argR, UInt nzcv ) argument
2527 UInt cond = INSN(15,12); local
2696 UInt cond = INSN(15,12); local
2735 UInt cond = INSN(15,12); local
4567 UInt cond = INSN(3,0); local
4652 IRExpr* cond = NULL; local
4687 IRExpr* cond local
[all...]
H A Dguest_arm_helpers.c474 UInt cond = cond_n_op >> 4; local
481 if (cond == ARMCondAL) return 1;
483 inv = cond & 1;
485 switch (cond) {
531 cond, cc_op, cc_dep1, cc_dep2, cc_dep3 );
H A Dguest_arm_toIR.c1094 static const HChar* name_ARMCondcode ( ARMCondcode cond )
1096 switch (cond) {
1117 static const HChar* nCC ( ARMCondcode cond ) {
1118 return name_ARMCondcode(cond);
1125 Ity_I32, the returned value is either 0 or 1. 'cond' must be
1129 static IRExpr* mk_armg_calculate_condition_dyn ( IRExpr* cond )
1131 vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I32);
1132 /* And 'cond' had better produce a value in which only bits 7:4 are
1136 "(cond << 4) | stored-operation".
1137 However, as per comments above, 'cond' mus
4197 IRTemp cond; local
4263 IRTemp cond, acc, tmp; local
4835 IRTemp res, arg_m, arg_n, cond, tmp; local
19071 UInt cond = INSN0(11,8); local
20585 UInt cond = INSN0(9,6); local
[all...]
H A Dguest_mips_toIR.c1701 /* Function that returns a string that represent mips cond
1736 UInt cond = get_cond(cins); local
1738 if (FC == 0x3) { /* C.cond.fmt */
1741 case 0x10: { /* C.cond.S */
1742 DIP("c.%s.s %d, f%d, f%d", showCondCode(cond), fpc_cc, fs, ft);
1790 switch (cond) {
1887 switch (cond) {
1950 case 0x11: { /* C.cond.D */
1951 DIP("c.%s.d %d, f%d, f%d", showCondCode(cond), fpc_cc, fs, ft);
1986 switch (cond) {
[all...]
H A Dguest_ppc_toIR.c5856 IRExpr *argLe, *argRe, *cond, *tmp; local
5909 cond = const0;
5912 cond = binop(opOR, tmp, cond);
5916 cond = binop(opOR, tmp, cond);
5920 cond = binop(opOR, tmp, cond);
5924 cond = binop(opOR, tmp, cond);
[all...]
H A Dguest_s390_helpers.c1846 ULong cond, cc_op; local
1858 cond = cond_expr->Iex.Const.con->Ico.U64;
1861 vassert(cond <= 15);
1866 | cond | 8 | 4 | 2 | 1 |
1875 cc == 0 --> cc_dep1 == cc_dep2 (cond == 8)
1876 cc == 1 --> cc_dep1 < cc_dep2 (cond == 4)
1877 cc == 2 --> cc_dep1 > cc_dep2 (cond == 2)
1879 Because cc == 3 cannot occur the rightmost bit of cond is
1882 if (cond == 8 || cond
[all...]
H A Dguest_s390_toIR.c3615 IRTemp cond = newTemp(Ity_I32); local
3626 assign(cond, s390_call_calculate_cond(r1));
3627 if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
3640 IRTemp cond = newTemp(Ity_I32); local
3647 assign(cond, s390_call_calculate_cond(r1));
3648 if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
3775 IRTemp cond = newTemp(Ity_I32); local
3783 assign(cond, s390_call_calculate_cond(r1));
3784 if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)),
3798 IRTemp cond local
4054 IRTemp cond = newTemp(Ity_I32); local
4078 IRTemp cond = newTemp(Ity_I32); local
4102 IRTemp cond = newTemp(Ity_I32); local
4128 IRTemp cond = newTemp(Ity_I32); local
4154 IRTemp cond = newTemp(Ity_I32); local
4178 IRTemp cond = newTemp(Ity_I32); local
4202 IRTemp cond = newTemp(Ity_I32); local
4227 IRTemp cond = newTemp(Ity_I32); local
4701 IRTemp cond = newTemp(Ity_I32); local
4725 IRTemp cond = newTemp(Ity_I32); local
4749 IRTemp cond = newTemp(Ity_I32); local
4774 IRTemp cond = newTemp(Ity_I32); local
4799 IRTemp cond = newTemp(Ity_I32); local
4823 IRTemp cond = newTemp(Ity_I32); local
4847 IRTemp cond = newTemp(Ity_I32); local
4872 IRTemp cond = newTemp(Ity_I32); local
10846 IRTemp cond; local
10945 IRTemp cond; local
13716 IRExpr *cond, *addr, *byte2, *byte3, *byte4; local
[all...]
H A Dguest_x86_helpers.c639 UInt x86g_calculate_condition ( UInt/*X86Condcode*/ cond, argument
648 UInt inv = cond & 1;
652 tab_cond[cc_op][cond]++;
657 switch (cond) {
709 cond, cc_op, cc_dep1, cc_dep2, cc_ndep );
803 IRExpr *cond, *cc_op, *cc_dep1, *cc_dep2; local
805 cond = args[0];
812 if (isU32(cc_op, X86G_CC_OP_ADDL) && isU32(cond, X86CondZ)) {
822 if (isU32(cc_op, X86G_CC_OP_SUBL) && isU32(cond, X86CondZ)) {
827 if (isU32(cc_op, X86G_CC_OP_SUBL) && isU32(cond, X86CondN
[all...]
H A Dguest_x86_toIR.c807 static IRExpr* mk_x86g_calculate_condition ( X86Condcode cond )
810 = mkIRExprVec_5( mkU32(cond),
1062 static const HChar* name_X86Condcode ( X86Condcode cond )
1064 switch (cond) {
1087 X86Condcode positiveIse_X86Condcode ( X86Condcode cond, argument
1090 vassert(cond >= X86CondO && cond <= X86CondNLE);
1091 if (cond & 1) {
1093 return cond-1;
1096 return cond;
1371 jcc_01( DisResult* dres, X86Condcode cond, Addr32 d32_false, Addr32 d32_true ) argument
3283 dis_REP_op( DisResult* dres, X86Condcode cond, void (*dis_OP)(Int, IRTemp), Int sz, Addr32 eip, Addr32 eip_next, const HChar* name ) argument
3608 maybe_put_ST( IRTemp cond, Int i, IRExpr* value ) argument
6652 IRTemp cond = newTemp(Ity_I1); local
6743 dis_cmov_E_G( UChar sorb, Int sz, X86Condcode cond, Int delta0 ) argument
13519 IRExpr* cond = NULL; local
[all...]
H A Dhost_amd64_defs.c178 const HChar* showAMD64CondCode ( AMD64CondCode cond )
180 switch (cond) {
696 AMD64Instr* AMD64Instr_Call ( AMD64CondCode cond, Addr64 target, Int regparms, argument
700 i->Ain.Call.cond = cond;
710 AMD64CondCode cond, Bool toFastEP ) {
715 i->Ain.XDirect.cond = cond;
720 AMD64CondCode cond ) {
725 i->Ain.XIndir.cond
709 AMD64Instr_XDirect( Addr64 dstGA, AMD64AMode* amRIP, AMD64CondCode cond, Bool toFastEP ) argument
728 AMD64Instr_XAssisted( HReg dstGA, AMD64AMode* amRIP, AMD64CondCode cond, IRJumpKind jk ) argument
739 AMD64Instr_CMov64( AMD64CondCode cond, AMD64RM* src, HReg dst ) argument
776 AMD64Instr_Set64( AMD64CondCode cond, HReg dst ) argument
964 AMD64Instr_SseCMov( AMD64CondCode cond, HReg src, HReg dst ) argument
[all...]
H A Dhost_amd64_defs.h473 AMD64CondCode cond; member in struct:__anon31681::__anon31682::__anon31694
483 AMD64CondCode cond; /* can be Acc_ALWAYS */ member in struct:__anon31681::__anon31682::__anon31695
491 AMD64CondCode cond; /* can be Acc_ALWAYS */ member in struct:__anon31681::__anon31682::__anon31696
498 AMD64CondCode cond; /* can be Acc_ALWAYS */ member in struct:__anon31681::__anon31682::__anon31697
504 AMD64CondCode cond; member in struct:__anon31681::__anon31682::__anon31698
529 AMD64CondCode cond; member in struct:__anon31681::__anon31682::__anon31702
661 AMD64CondCode cond; member in struct:__anon31681::__anon31682::__anon31724
707 AMD64CondCode cond, Bool toFastEP );
709 AMD64CondCode cond );
711 AMD64CondCode cond, IRJumpKin
[all...]
H A Dhost_amd64_isel.c1528 AMD64CondCode cond = iselCondCode(env, e->Iex.Unop.arg); local
1529 addInstr(env, AMD64Instr_Set64(cond,dst));
1538 AMD64CondCode cond = iselCondCode(env, e->Iex.Unop.arg); local
1539 addInstr(env, AMD64Instr_Set64(cond,dst));
1863 && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) {
1868 AMD64CondCode cc = iselCondCode(env, e->Iex.ITE.cond);
3089 vassert(typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1);
3094 AMD64CondCode cc = iselCondCode(env, e->Iex.ITE.cond);
3702 AMD64CondCode cc = iselCondCode(env, e->Iex.ITE.cond);
4261 AMD64CondCode cc = iselCondCode(env, e->Iex.ITE.cond);
4476 AMD64CondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data); local
[all...]
H A Dhost_arm64_defs.c205 static const HChar* showARM64CondCode ( ARM64CondCode cond ) {
206 switch (cond) {
1419 ARM64CondCode cond, Bool toFastEP ) {
1424 i->ARM64in.XDirect.cond = cond;
1429 ARM64CondCode cond ) {
1434 i->ARM64in.XIndir.cond = cond;
1438 ARM64CondCode cond, IRJumpKind jk ) {
1443 i->ARM64in.XAssisted.cond
1418 ARM64Instr_XDirect( Addr64 dstGA, ARM64AMode* amPC, ARM64CondCode cond, Bool toFastEP ) argument
1437 ARM64Instr_XAssisted( HReg dstGA, ARM64AMode* amPC, ARM64CondCode cond, IRJumpKind jk ) argument
1457 ARM64Instr_Call( ARM64CondCode cond, HWord target, Int nArgRegs, RetLoc rloc ) argument
4554 UInt cond = (UInt)i->ARM64in.CSel.cond; local
[all...]
H A Dhost_arm64_defs.h709 ARM64CondCode cond; /* can be ARM64cc_AL */ member in struct:__anon31763::__anon31764::__anon31777
717 ARM64CondCode cond; /* can be ARM64cc_AL */ member in struct:__anon31763::__anon31764::__anon31778
724 ARM64CondCode cond; /* can be ARM64cc_AL */ member in struct:__anon31763::__anon31764::__anon31779
727 /* CSEL: dst = if cond then argL else argR. cond may be anything. */
732 ARM64CondCode cond; member in struct:__anon31763::__anon31764::__anon31780
739 ARM64CondCode cond; member in struct:__anon31763::__anon31764::__anon31781
901 //ZZ ARMCondCode cond;
908 //ZZ ARMCondCode cond;
1044 ARM64CondCode cond, Boo
[all...]
H A Dhost_arm_defs.c194 const HChar* showARMCondCode ( ARMCondCode cond ) {
195 switch (cond) {
1195 ARMCondCode cond, Bool toFastEP ) {
1200 i->ARMin.XDirect.cond = cond;
1205 ARMCondCode cond ) {
1210 i->ARMin.XIndir.cond = cond;
1214 ARMCondCode cond, IRJumpKind jk ) {
1219 i->ARMin.XAssisted.cond
1194 ARMInstr_XDirect( Addr32 dstGA, ARMAMode1* amR15T, ARMCondCode cond, Bool toFastEP ) argument
1213 ARMInstr_XAssisted( HReg dstGA, ARMAMode1* amR15T, ARMCondCode cond, IRJumpKind jk ) argument
1223 ARMInstr_CMov( ARMCondCode cond, HReg dst, ARMRI84* src ) argument
1232 ARMInstr_Call( ARMCondCode cond, HWord target, Int nArgRegs, RetLoc rloc ) argument
1320 ARMInstr_VCMovD( ARMCondCode cond, HReg dst, HReg src ) argument
1329 ARMInstr_VCMovS( ARMCondCode cond, HReg dst, HReg src ) argument
1467 ARMInstr_NCMovQ( ARMCondCode cond, HReg dst, HReg src ) argument
[all...]
H A Dhost_arm_defs.h698 ARMCondCode cond; /* can be ARMcc_AL */ member in struct:__anon31854::__anon31855::__anon31866
706 ARMCondCode cond; /* can be ARMcc_AL */ member in struct:__anon31854::__anon31855::__anon31867
713 ARMCondCode cond; /* can be ARMcc_AL */ member in struct:__anon31854::__anon31855::__anon31868
719 ARMCondCode cond; member in struct:__anon31854::__anon31855::__anon31869
726 ARMCondCode cond; member in struct:__anon31854::__anon31855::__anon31870
806 ARMCondCode cond; member in struct:__anon31854::__anon31855::__anon31881
813 ARMCondCode cond; member in struct:__anon31854::__anon31855::__anon31882
934 ARMCondCode cond; member in struct:__anon31854::__anon31855::__anon31900
973 ARMCondCode cond, Bool toFastEP );
975 ARMCondCode cond );
[all...]

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