/external/clang/test/CXX/basic/basic.start/basic.start.main/ |
H A D | p2.cpp | 41 #elif TEST3
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/external/clang/test/CodeGenCXX/ |
H A D | 2010-06-22-BitfieldInit.cpp | 12 } TEST3; typedef in typeref:struct:_TEST3 14 TEST3 test =
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/external/clang/test/Driver/ |
H A D | darwin-version.c | 27 #ifdef TEST3
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/external/clang/test/Frontend/ |
H A D | verify.c | 66 #ifdef TEST3 67 #ifndef TEST3 // expected-note {{line_67}} 71 #elif defined(TEST3) // expected-note {{line_71}} 76 # ifndef TEST3 // expected-note {{line_76_ignored}}
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H A D | verify3.c | 28 #ifdef TEST3
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/external/llvm/test/MC/ARM/ |
H A D | eh-directive-multiple-offsets.s | 67 @ TEST3: Check .setfp, .pad, .setfp directive. 69 .section .TEST3 91 @ CHECK: Name: .ARM.extab.TEST3
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H A D | eh-directive-pad.s | 89 @ TEST3 91 .section .TEST3 122 @ CHECK: Name: .ARM.extab.TEST3
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H A D | eh-directive-save.s | 160 @ TEST3 162 .section .TEST3 206 @ CHECK: Name: .ARM.extab.TEST3
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H A D | eh-directive-setfp-diagnostics.s | 44 @ TEST3: .setfp with bad fp register
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H A D | eh-directive-setfp.s | 98 @ TEST3 100 .section .TEST3 132 @ CHECK: Name: .ARM.extab.TEST3
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/external/llvm/test/MC/AsmParser/ |
H A D | directive_ascii.s | 17 # CHECK: TEST3: 22 TEST3: label
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H A D | directive_fill.s | 21 # CHECK: TEST3 26 TEST3: label
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H A D | directive_values.s | 18 # CHECK: TEST3: 20 TEST3: label
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/external/valgrind/main/none/tests/mips64/ |
H A D | arithmetic_instruction.c | 67 TEST3("clo $t0, $t1", reg_val1[i], t0, t1); 74 TEST3("clz $t0, $t1", reg_val1[i], t0, t1); 123 TEST3("dclo $t0, $t1", reg_val1[i], t0, t1); 124 TEST3("dclo $v0, $v1", reg_val2[i], v0, v1); 129 TEST3("dclz $t0, $t1", reg_val1[i], t0, t1); 130 TEST3("dclz $v0, $v1", reg_val2[i], v0, v1); 281 TEST3("seb $t0, $t1", reg_val1[i], t0, t1); 290 TEST3("seh $t0, $t1", reg_val1[i], t0, t1);
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H A D | branch_and_jump_instructions.c | 107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \ macro 193 TEST3("beq", 0, 0, 1, 2, 3, 4); 194 TEST3("beq", 1, 1, 1, 3, 4, 5); 195 TEST3("beq", 2, 0xffffffff, 0xffffffff, 4, 5, 6); 196 TEST3("beq", 3, 0xffffffff, 0xfffffffe, 5, 6, 7); 197 TEST3("beq", 4, 0xfffffffe, 0xffffffff, 6, 7, 8); 198 TEST3("beq", 5, 0xffffffff, 0xffffffff, 7, 8, 9); 199 TEST3("beq", 6, 0x5, 0x5, 8, 9, 10); 200 TEST3("beq", 7, -3, -4, 9, 10, 11); 201 TEST3("be [all...] |
H A D | fpu_load_store.c | 15 TEST3("ldc1", i, reg_val1); 18 TEST3("ldc1", i, reg_val2);
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H A D | macro_int.h | 35 #define TEST3(instruction, RSval, RD, RS) \ macro
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H A D | macro_load_store.h | 47 #define TEST3(instruction, offset, mem) \ macro
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H A D | move_instructions.c | 92 #define TEST3(instruction, FD, FS, cc, offset) \ macro 207 TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 0); 208 TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 8); 209 TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 16); 210 TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 24); 211 TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 32) 212 TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 40) 213 TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 48) 214 TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 56) 215 TEST3("mov [all...] |