Searched refs:msub (Results 1 - 25 of 41) sorted by last modified time

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/external/valgrind/main/none/tests/mips64/
H A Dfpu_arithmetic.stdout.exp1731 msub.s 347857.000000 -347856.500000 0.000000 -4578.500000
1732 msub.s -147883.000000 356047.500000 456.250000 456.250000
1733 msub.s 103.000000 -1.000000 3.000000 34.031250
1734 msub.s -4602.000000 23.062500 -1.000000 4578.750000
1735 msub.s 240536.000000 1752.000000 1384.500000 175.000000
1736 msub.s -776.000000 0.015625 -7.250000 107.000000
1737 msub.s -456249999360.000000 0.031250 1000000000.000000 -456.250000
1738 msub.s 290515.000000 -248562.750000 -5786.500000 -7.250000
1739 msub.s -6095717.000000 1384.500000 1752.000000 -3478.500000
1740 msub
[all...]
/external/vixl/src/a64/
H A Dassembler-a64.cc905 void Assembler::msub(const Register& rd, function in class:vixl::Assembler
H A Dassembler-a64.h1060 void msub(const Register& rd,
H A Dmacro-assembler-a64.h844 msub(rd, rn, rm, ra);
/external/vixl/test/
H A Dtest-assembler-a64.cc1179 TEST(msub) {
H A Dtest-disasm-a64.cc448 TEST(msub) {
451 COMPARE(msub(w0, w1, w2, w3), "msub w0, w1, w2, w3");
452 COMPARE(msub(w30, w21, w22, w16), "msub w30, w21, w22, w16");
453 COMPARE(msub(x0, x1, x2, x3), "msub x0, x1, x2, x3");
454 COMPARE(msub(x30, x21, x22, x16), "msub x30, x21, x22, x16");
/external/llvm/test/MC/AArch64/
H A Darm64-arithmetic-encoding.s462 msub w1, w2, w3, w4
463 msub x1, x2, x3, x4
471 ; CHECK: msub w1, w2, w3, w4 ; encoding: [0x41,0x90,0x03,0x1b]
472 ; CHECK: msub x1, x2, x3, x4 ; encoding: [0x41,0x90,0x03,0x9b]
H A Dbasic-a64-instructions.s1558 msub w1, w3, w7, w4
1559 msub wzr, w0, w9, w11
1560 msub w13, wzr, w4, w4
1561 msub w19, w30, wzr, w29
1562 msub w4, w5, w6, wzr
1563 // CHECK: msub w1, w3, w7, w4 // encoding: [0x61,0x90,0x07,0x1b]
1564 // CHECK: msub wzr, w0, w9, w11 // encoding: [0x1f,0xac,0x09,0x1b]
1565 // CHECK: msub w13, wzr, w4, w4 // encoding: [0xed,0x93,0x04,0x1b]
1566 // CHECK: msub w19, w30, wzr, w29 // encoding: [0xd3,0xf7,0x1f,0x1b]
1569 msub x
[all...]
/external/llvm/test/MC/Mips/
H A Dmicromips-fpu-instructions.s66 # CHECK-EL: msub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x21,0x11]
67 # CHECK-EL: msub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x29,0x11]
129 # CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21]
130 # CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29]
188 msub.s $f2, $f4, $f6, $f8
189 msub.d $f2, $f4, $f6, $f8
H A Dmicromips-multiply-instructions.s14 # CHECK-EL: msub $4, $5 # encoding: [0xa4,0x00,0x3c,0xeb]
21 # CHECK-EB: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c]
25 msub $4, $5
H A Dmips-alu-instructions.s84 # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
109 msub $6,$7
H A Dmips-dsp-instructions.s33 # CHECK: msub $ac3, $10, $11 # encoding: [0x71,0x4b,0x18,0x04]
44 # CHECK: msub $10, $11 # encoding: [0x71,0x4b,0x00,0x04]
81 msub $ac3, $10, $11
92 msub $10, $11
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips5-wrong-error.s37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips32.s39 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips32r2.s46 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
47 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
48 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips5-wrong-error.s37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5-wrong-error.s37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
/external/llvm/test/MC/Mips/mips32/
H A Dinvalid-mips32r2.s18 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dvalid.s91 msub $s7,$k1
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s104 msub $s7,$k1
105 msub.d $f10,$f1,$f31,$f18
106 msub.s $f12,$f19,$f10,$f16
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips32.s24 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips32r2.s10 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips5-wrong-error.s37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction
H A Dinvalid-mips64.s20 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips64r2.s25 msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

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