/external/webrtc/src/common_audio/signal_processing/ |
H A D | spl_sqrt_floor.s | 9 @ Registers touched: r1, r2 16 mov r1, #3 << 30 23 adc r2, r1, r2, lsl #1 27 adc r2, r1, r2, lsl #1 31 adc r2, r1, r2, lsl #1 35 adc r2, r1, r2, lsl #1 39 adc r2, r1, r2, lsl #1 43 adc r2, r1, r2, lsl #1 47 adc r2, r1, r2, lsl #1 51 adc r2, r1, r [all...] |
/external/webrtc/src/modules/audio_coding/codecs/isac/fix/source/ |
H A D | lattice_armv7.S | 19 @ r1: &ar_f_Q0 40 add r1, #2 @ &ar_f_Q0[1] 48 ldrh r5, [r1] @ tmpAR = ar_f_Q0[n+1] 73 strh r5, [r1], #2 @ Output: ar_f_Q0[n+1] = tmpAR;
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H A D | lattice_neon.S | 48 vdup.32 d29, r1 @ Initialize Neon register with input1 145 smulwb r5, r7, r1 @ tmp32a = *ptr0 * input1 >> 16
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H A D | lpc_masking_model_neon.S | 33 str r1, [r13, #8] 61 mov r1, r6 @ j = i; 79 add r1, r1, #2 87 cmp r0, r1 @ Compare lpc_order to j. 91 bic r1, r10, #1 93 add r2, r1, r2 154 vmov.s32 r1, d1[1] @ Store # of sign bits of only the 32 MSBs. 166 add r1, r12, r1 [all...] |
H A D | pitch_filter_armv6.S | 64 @ r1: gain 100 smulbb r5, r1, r7
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/external/wpa_supplicant_8/hostapd/src/ap/ |
H A D | wpa_auth_ft.c | 181 struct wpa_ft_pmk_r1_sa *r1, *r1prev; local 191 r1 = cache->pmk_r1; 192 while (r1) { 193 r1prev = r1; 194 r1 = r1->next; 258 struct wpa_ft_pmk_r1_sa *r1; local 262 r1 = os_zalloc(sizeof(*r1)); 263 if (r1 283 struct wpa_ft_pmk_r1_sa *r1; local [all...] |
/external/wpa_supplicant_8/src/ap/ |
H A D | wpa_auth_ft.c | 181 struct wpa_ft_pmk_r1_sa *r1, *r1prev; local 191 r1 = cache->pmk_r1; 192 while (r1) { 193 r1prev = r1; 194 r1 = r1->next; 258 struct wpa_ft_pmk_r1_sa *r1; local 262 r1 = os_zalloc(sizeof(*r1)); 263 if (r1 283 struct wpa_ft_pmk_r1_sa *r1; local [all...] |
/external/wpa_supplicant_8/wpa_supplicant/src/ap/ |
H A D | wpa_auth_ft.c | 181 struct wpa_ft_pmk_r1_sa *r1, *r1prev; local 191 r1 = cache->pmk_r1; 192 while (r1) { 193 r1prev = r1; 194 r1 = r1->next; 258 struct wpa_ft_pmk_r1_sa *r1; local 262 r1 = os_zalloc(sizeof(*r1)); 263 if (r1 283 struct wpa_ft_pmk_r1_sa *r1; local [all...] |
/external/valgrind/main/none/tests/s390x/ |
H A D | and.c | 5 #define nihh(r1,i2) ".long 0xa5" #r1 "4" #i2 "\n\t" 6 #define nihl(r1,i2) ".long 0xa5" #r1 "5" #i2 "\n\t" 7 #define nilh(r1,i2) ".long 0xa5" #r1 "6" #i2 "\n\t" 8 #define nill(r1,i2) ".long 0xa5" #r1 "7" #i2 "\n\t"
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H A D | bfp-1.c | 31 register float r1 asm("f1") = f1; 34 __asm__ volatile ("aebr %[r1],%[r2]\n\t" 35 : [r1] "+f"(r1) 37 printf("%f + %f = %f\n", f1, f2, r1); 42 register float r1 asm("f1") = f1; 45 __asm__ volatile ("sebr %[r1],%[r2]\n\t" 46 : [r1] "+f"(r1) 48 printf("%f - %f = %f\n", f1, f2, r1); [all...] |
H A D | bfp-3.c | 8 float r1 = v1; local 10 __asm__ volatile("maebr %[r1],%[r3],%[r2]" 11 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3)); 12 printf("maebr %f * %f + %f -> %f\n", v2, v3, v1, r1); 17 double r1 = v1; local 19 __asm__ volatile("madbr %[r1],%[r3],%[r2]" 20 : [r1]"+f"(r1) : [r2]"f"(v2), [r3]"f"(v3)); 21 printf("madbr %f * %f + %f -> %f\n", v2, v3, v1, r1); 26 float r1 = v1; local 35 double r1 = v1; local [all...] |
H A D | bfp-4.c | 9 __asm__ volatile("cebr %[r1],%[r2]\n\t" 12 : [psw]"=d"(cc) : [r1]"f"(v1), [r2]"f"(v2) : "cc"); 25 __asm__ volatile("cdbr %[r1],%[r2]\n\t" 28 : [psw]"=d"(cc) : [r1]"f"(v1), [r2]"f"(v2) : "cc");
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H A D | clcl.c | 20 uint64_t r1; member in struct:__anon33227 29 do_clcl(uint64_t r1, uint64_t r1p1, uint64_t r2, uint64_t r2p1) argument 33 register uint64_t a1 asm ("2") = r1; 46 regs.r1 = a1; 60 result.addr1 = regs.r1; 78 uint64_t r1, r1p1, r2, r2p1; local 86 r1 = (uint64_t)addr1; 92 regs = do_clcl(r1, r1p1, r2, r2p1); 97 printf("FAIL: r1[0:39] modified (unused bits 0)\n"); 110 regs = do_clcl(r1, r1p [all...] |
H A D | comp-1.c | 14 #define RIL_RI(op1,r1,op2,i2) \ 15 ".short 0x" #op1 #r1 #op2 "\n\t" \
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H A D | comp-2.c | 14 #define RIL_RU(op1,r1,op2,i2) \ 15 ".short 0x" #op1 #r1 #op2 "\n\t" \
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H A D | icm.c | 3 #define icm(r1, mask, b) do {\ 7 :: "a" (r1), "a" (b) \ 11 #define icmh(r1, mask, b) do {\ 15 :: "a" (r1), "a" (b) \
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H A D | insert.c | 5 #define iihh(r1,i2) ".long 0xa5" #r1 "0" #i2 "\n\t" 6 #define iihl(r1,i2) ".long 0xa5" #r1 "1" #i2 "\n\t" 7 #define iilh(r1,i2) ".long 0xa5" #r1 "2" #i2 "\n\t" 8 #define iill(r1,i2) ".long 0xa5" #r1 "3" #i2 "\n\t"
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H A D | mvcl.c | 20 uint64_t r1; member in struct:__anon33240 30 do_mvcl(uint64_t r1, uint64_t r1p1, uint64_t r2, uint64_t r2p1) argument 34 register uint64_t a1 asm ("2") = r1; 47 regs.r1 = a1; 61 result.addr1 = regs.r1; 79 uint64_t r1, r1p1, r2, r2p1; local 90 r1 = (uint64_t)addr1; 96 regs = do_mvcl(r1, r1p1, r2, r2p1); 101 printf("FAIL: r1[0:39] modified (unused bits 0)\n"); 115 regs = do_mvcl(r1, r1p [all...] |
H A D | opcodes.h | 19 #define RIL_RI(op1,r1,op2,i2) \ 20 ".short 0x" #op1 #r1 #op2 "\n\t" \ 22 #define RIE_RRI0(op1,r1,r3,i2,u0,op2) \ 23 ".short 0x" #op1 #r1 #r3 "\n\t" \ 25 #define RRF_R0RR2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t" 29 #define RXY_RRRD(op1,r1,x2,b2,dl2,dh2,op2) \ 30 ".short 0x" #op1 #r1 #x2 "\n\t" \ 32 #define RIL_RU(op1,r1,op2,i2) \ 33 ".short 0x" #op1 #r1 #op [all...] |
H A D | or.c | 5 #define oihh(r1,i2) ".long 0xa5" #r1 "8" #i2 "\n\t" 6 #define oihl(r1,i2) ".long 0xa5" #r1 "9" #i2 "\n\t" 7 #define oilh(r1,i2) ".long 0xa5" #r1 "a" #i2 "\n\t" 8 #define oill(r1,i2) ".long 0xa5" #r1 "b" #i2 "\n\t"
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H A D | rounding-5.c | 39 __asm__ volatile("cefbr %[r1],%[r2]" : [r1] "=f"(out) : [r2] "d"(i32)); 49 __asm__ volatile("cegbr %[r1],%[r2]" : [r1] "=f"(out) : [r2] "d"(i64)); 59 __asm__ volatile("cdgbr %[r1],%[r2]" : [r1] "=f"(out) : [r2] "d"(i64));
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H A D | rxsbg.c | 6 register unsigned long r1 asm ("1") = _r1; \ 12 : "+d" (r1), "=d" (cc) \ 13 : "d" (r1), "d" (r2) \ 15 printf(#insn " r1(==%16.16lX),r2(==%16.16lX),0x" #i3 ",0x" #i4 ",0x" #i5 " = %16.16lX (cc=%d)\n", _r1, _r2, r1, cc); \
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H A D | rxsbg.stdout.exp | 1 RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x00 = 0000000000000000 (cc=0) 2 RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) 3 RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2) 4 RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000000000000000 (cc=0) 5 RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) 6 RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2) 7 RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000000000000000 (cc=1) 8 RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000FFFFCCCCAAAA (cc=1) 9 RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) 10 RISBG r1( [all...] |
/external/valgrind/main/none/tests/x86/ |
H A D | incdec_alt.c | 7 int r1,r2,r3,r4,r5,r6,r7,r8,a1,a2; variable 21 "\tmovl %eax," VG_SYM(r1) "\n" 58 r1=r2=r3=r4=r5=r6=r7=r8=0; 60 printf("0x%08x\n",r1);
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H A D | sbbmisc.stdout.exp | 0 r1 = 94 93
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