Searched refs:regs (Results 1 - 25 of 321) sorted by last modified time

1234567891011>>

/external/zlib/src/contrib/masmx64/
H A Dinffasx64.asm42 mov [rax+8], rbp ; /* save regs rbp and rsp */
/external/webrtc/src/system_wrappers/source/android/
H A Dcpu-features.c349 int regs[4]; local
356 x86_cpuid(0, regs);
357 int vendorIsIntel = (regs[1] == VENDOR_INTEL_b &&
358 regs[2] == VENDOR_INTEL_c &&
359 regs[3] == VENDOR_INTEL_d);
361 x86_cpuid(1, regs);
362 if ((regs[2] & (1 << 9)) != 0) {
365 if ((regs[2] & (1 << 23)) != 0) {
368 if (vendorIsIntel && (regs[2] & (1 << 22)) != 0) {
/external/valgrind/main/none/tests/s390x/
H A Dclcl.c31 clcl_regs regs; local
46 regs.r1 = a1;
47 regs.r1p1 = l1;
48 regs.r2 = a2;
49 regs.r2p1 = l2;
50 regs.cc = cc;
52 return regs;
56 result_from_regs(clcl_regs regs) argument
60 result.addr1 = regs.r1;
61 result.len1 = regs
77 clcl_regs regs; local
[all...]
H A Dcu12.c80 cu12_t regs; local
98 regs.addr1 = (uint64_t)dest;
99 regs.len1 = dest_len;
100 regs.addr2 = (uint64_t)source;
101 regs.len2 = source_len;
102 regs.cc = cc;
104 return regs;
H A Dcu12_1.c80 cu12_t regs; local
98 regs.addr1 = (uint64_t)dest;
99 regs.len1 = dest_len;
100 regs.addr2 = (uint64_t)source;
101 regs.len2 = source_len;
102 regs.cc = cc;
104 return regs;
H A Dcu14.c80 cu14_t regs; local
98 regs.addr1 = (uint64_t)dest;
99 regs.len1 = dest_len;
100 regs.addr2 = (uint64_t)source;
101 regs.len2 = source_len;
102 regs.cc = cc;
104 return regs;
H A Dcu14_1.c80 cu14_t regs; local
98 regs.addr1 = (uint64_t)dest;
99 regs.len1 = dest_len;
100 regs.addr2 = (uint64_t)source;
101 regs.len2 = source_len;
102 regs.cc = cc;
104 return regs;
H A Dcu21.c71 cu21_t regs; local
89 regs.addr1 = (uint64_t)dest;
90 regs.len1 = dest_len;
91 regs.addr2 = (uint64_t)source;
92 regs.len2 = source_len;
93 regs.cc = cc;
95 return regs;
H A Dcu21_1.c71 cu21_t regs; local
89 regs.addr1 = (uint64_t)dest;
90 regs.len1 = dest_len;
91 regs.addr2 = (uint64_t)source;
92 regs.len2 = source_len;
93 regs.cc = cc;
95 return regs;
H A Dcu24.c58 cu24_t regs; local
76 regs.addr1 = (uint64_t)dest;
77 regs.len1 = dest_len;
78 regs.addr2 = (uint64_t)source;
79 regs.len2 = source_len;
80 regs.cc = cc;
82 return regs;
H A Dcu24_1.c58 cu24_t regs; local
76 regs.addr1 = (uint64_t)dest;
77 regs.len1 = dest_len;
78 regs.addr2 = (uint64_t)source;
79 regs.len2 = source_len;
80 regs.cc = cc;
82 return regs;
H A Dcu41.c72 cu41_t regs; local
90 regs.addr1 = (uint64_t)dest;
91 regs.len1 = dest_len;
92 regs.addr2 = (uint64_t)source;
93 regs.len2 = source_len;
94 regs.cc = cc;
96 return regs;
H A Dcu42.c61 cu42_t regs; local
79 regs.addr1 = (uint64_t)dest;
80 regs.len1 = dest_len;
81 regs.addr2 = (uint64_t)source;
82 regs.len2 = source_len;
83 regs.cc = cc;
85 return regs;
H A Dmvcl.c32 mvcl_regs regs; local
47 regs.r1 = a1;
48 regs.r1p1 = l1;
49 regs.r2 = a2;
50 regs.r2p1 = l2;
51 regs.cc = cc;
53 return regs;
57 result_from_regs(mvcl_regs regs) argument
61 result.addr1 = regs.r1;
62 result.len1 = regs
78 mvcl_regs regs; local
[all...]
H A Dtre.c22 tre_regs regs; local
36 regs.addr = a1;
37 regs.len = l1;
38 regs.tabaddr = a2;
39 regs.testbyte = param;
40 regs.cc = cc;
42 return regs;
47 tre_regs regs; local
50 regs = tre(tran_table, srcaddr, len, test);
52 if ((uint64_t)tran_table != regs
[all...]
H A Dtroo.c29 troo_regs regs; local
46 regs.srcaddr = srcaddr;
47 regs.len = length;
48 regs.desaddr = desaddr;
49 regs.tabaddr = codepage2;
50 regs.testbyte = test_byte;
51 regs.cc = cc;
52 return regs;
58 troo_regs regs; local
66 regs
[all...]
H A Dtrot.c30 trot_regs regs; local
47 regs.srcaddr = srcaddr;
48 regs.len = length;
49 regs.desaddr = desaddr;
50 regs.tabaddr = codepage2;
51 regs.testbyte = test_byte;
52 regs.cc = cc;
53 return regs;
59 trot_regs regs; local
67 regs
[all...]
H A Dtrto.c29 trto_regs regs; local
46 regs.srcaddr = srcaddr;
47 regs.len = length;
48 regs.desaddr = desaddr;
49 regs.tabaddr = codepage2;
50 regs.testbyte = test_byte;
51 regs.cc = cc;
52 return regs;
58 trto_regs regs; local
66 regs
[all...]
H A Dtrtt.c30 trtt_regs regs; local
47 regs.srcaddr = srcaddr;
48 regs.len = length;
49 regs.desaddr = desaddr;
50 regs.tabaddr = codepage2;
51 regs.testbyte = test_byte;
52 regs.cc = cc;
54 return regs;
60 trtt_regs regs; local
68 regs
[all...]
/external/vixl/src/a64/
H A Dassembler-a64.cc2255 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; local
2257 for (unsigned i = 0; i < sizeof(regs) / sizeof(regs[0]); i++) {
2258 if (regs[i].IsRegister()) {
2260 unique_regs |= regs[i].Bit();
2261 } else if (regs[i].IsFPRegister()) {
2263 unique_fpregs |= regs[i].Bit();
2265 VIXL_ASSERT(!regs[i].IsValid());
H A Dmacro-assembler-a64.cc1470 const CPURegister regs[] = {reg1, reg2, reg3, reg4};
1472 for (unsigned i = 0; i < (sizeof(regs) / sizeof(regs[0])); i++) {
1473 if (regs[i].IsRegister()) {
1474 exclude |= regs[i].Bit();
1475 } else if (regs[i].IsFPRegister()) {
1476 excludefp |= regs[i].Bit();
1478 VIXL_ASSERT(regs[i].IsNone());
1508 RegList regs) {
1509 available->set_list(available->list() | regs);
1507 ReleaseByRegList(CPURegList* available, RegList regs) argument
1513 IncludeByRegList(CPURegList* available, RegList regs) argument
[all...]
H A Dmacro-assembler-a64.h272 void PushXRegList(RegList regs) { argument
273 PushSizeRegList(regs, kXRegSize);
275 void PopXRegList(RegList regs) { argument
276 PopSizeRegList(regs, kXRegSize);
278 void PushWRegList(RegList regs) { argument
279 PushSizeRegList(regs, kWRegSize);
281 void PopWRegList(RegList regs) { argument
282 PopSizeRegList(regs, kWRegSize);
284 inline void PushDRegList(RegList regs) { argument
285 PushSizeRegList(regs, kDRegSiz
287 PopDRegList(RegList regs) argument
290 PushSRegList(RegList regs) argument
293 PopSRegList(RegList regs) argument
[all...]
/external/vixl/test/examples/
H A Dtest-examples.cc75 void GenerateTestWrapper(MacroAssembler* masm, RegisterDump *regs) { argument
78 regs->Dump(masm);
156 RegisterDump regs; \
160 GenerateTestWrapper(&masm, &regs); \
172 assert(static_cast<uint64_t>(regs.xreg(0)) == FactorialC(N)); \
197 assert(static_cast<uint64_t>(regs.xreg(0)) == FactorialC(N)); \
224 assert(regs.dreg(0) == Add3DoubleC(A, B, C)); \
250 assert(regs.dreg(0) == Add4DoubleC(A, B, C, D)); \
276 assert(regs.xreg(0) == SumArrayC(Array, ARRAY_SIZE(Array))); \
305 assert(regs
[all...]
/external/webp/src/dsp/
H A Dcpu-features.c349 int regs[4]; local
356 x86_cpuid(0, regs);
357 int vendorIsIntel = (regs[1] == VENDOR_INTEL_b &&
358 regs[2] == VENDOR_INTEL_c &&
359 regs[3] == VENDOR_INTEL_d);
361 x86_cpuid(1, regs);
362 if ((regs[2] & (1 << 9)) != 0) {
365 if ((regs[2] & (1 << 23)) != 0) {
368 if (vendorIsIntel && (regs[2] & (1 << 22)) != 0) {
/external/valgrind/main/VEX/priv/
H A Dguest_arm_toIR.c82 which mean nothing natively (are no-ops as far as regs/mem are
8336 UInt regs = 1; local
8430 regs = 2;
8432 for (r = 0; r < regs; r++) {
8484 for (r = 0; r < regs; r++) {
8524 if (fB == BITS4(0,0,1,0) // Dd, Dd+1, Dd+2, Dd+3 inc = 1 regs = 4
8525 || fB == BITS4(0,1,1,0) // Dd, Dd+1, Dd+2 inc = 1 regs = 3
8526 || fB == BITS4(0,1,1,1) // Dd inc = 2 regs = 1
8527 || fB == BITS4(1,0,1,0)) { // Dd, Dd+1 inc = 1 regs = 2
8529 // meaning for the VLD1/VST1 cases. 'regs' i
[all...]

Completed in 281 milliseconds

1234567891011>>