/external/wpa_supplicant_8/hostapd/src/wps/ |
H A D | wps_upnp_ssdp.c | 818 struct rtentry rt; local 824 os_memset(&rt, 0, sizeof(rt)); 829 rt.rt_dev = (char *) net_if; 830 sin = aliasing_hide_typecast(&rt.rt_dst, struct sockaddr_in); 834 sin = aliasing_hide_typecast(&rt.rt_genmask, struct sockaddr_in); 838 rt.rt_flags = RTF_UP; 839 if (ioctl(sock, SIOCADDRT, &rt) < 0) {
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/external/wpa_supplicant_8/src/wps/ |
H A D | wps_upnp_ssdp.c | 818 struct rtentry rt; local 824 os_memset(&rt, 0, sizeof(rt)); 829 rt.rt_dev = (char *) net_if; 830 sin = aliasing_hide_typecast(&rt.rt_dst, struct sockaddr_in); 834 sin = aliasing_hide_typecast(&rt.rt_genmask, struct sockaddr_in); 838 rt.rt_flags = RTF_UP; 839 if (ioctl(sock, SIOCADDRT, &rt) < 0) {
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/external/wpa_supplicant_8/wpa_supplicant/src/wps/ |
H A D | wps_upnp_ssdp.c | 818 struct rtentry rt; local 824 os_memset(&rt, 0, sizeof(rt)); 829 rt.rt_dev = (char *) net_if; 830 sin = aliasing_hide_typecast(&rt.rt_dst, struct sockaddr_in); 834 sin = aliasing_hide_typecast(&rt.rt_genmask, struct sockaddr_in); 838 rt.rt_flags = RTF_UP; 839 if (ioctl(sock, SIOCADDRT, &rt) < 0) {
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/external/valgrind/main/none/tests/mips64/ |
H A D | logical_instructions.stdout.exp | 1 and $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb1f740b4 2 and $s0, $s1, $s2 :: rd 0x1284020, rs 0x12bd6aa, rt 0xa2a6ec661ba84121 3 and $t0, $t1, $t2 :: rd 0x0, rs 0x0, rt 0xffffffffb5365d03 4 and $s0, $s1, $s2 :: rd 0x4c834002122303, rs 0x7e876382d2ab13, rt 0x614d9b445f12236b 5 and $t0, $t1, $t2 :: rd 0x8003b4a, rs 0x9823b6e, rt 0xffffffffb8757bda 6 and $s0, $s1, $s2 :: rd 0x1328080203050071, rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75 7 and $t0, $t1, $t2 :: rd 0xc002649, rs 0xd4326d9, rt 0xffffffffbcb4666d 8 and $s0, $s1, $s2 :: rd 0x20044c571216a462, rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666 9 and $t0, $t1, $t2 :: rd 0x2003648, rs 0x130476dc, rt 0xffffffffa2f33668 10 and $s0, $s1, $s2 :: rd 0x40a040000401a502, rs 0x42b0c0a28677b502, rt [all...] |
H A D | cvm_ins.stdout.exp | 1 exts $t1, $t2, 1, 7 :: rt 0x0 rs 0x0, p 0x00000001, lenm1 0x00000007 2 exts $t1, $t2, 1, 7 :: rt 0x6e rs 0x130476dc, p 0x00000001, lenm1 0x00000007 3 exts $t1, $t2, 1, 7 :: rt 0xffffffffffffffdc rs 0x2608edb8, p 0x00000001, lenm1 0x00000007 4 exts $t1, $t2, 1, 7 :: rt 0xffffffffffffffb2 rs 0x350c9b64, p 0x00000001, lenm1 0x00000007 5 exts $t1, $t2, 1, 7 :: rt 0xffffffffffffffb8 rs 0x4c11db70, p 0x00000001, lenm1 0x00000007 6 exts $t1, $t2, 1, 7 :: rt 0xffffffffffffffd6 rs 0x5f15adac, p 0x00000001, lenm1 0x00000007 7 exts $t1, $t2, 1, 7 :: rt 0x64 rs 0x6a1936c8, p 0x00000001, lenm1 0x00000007 8 exts $t1, $t2, 1, 7 :: rt 0xa rs 0x791d4014, p 0x00000001, lenm1 0x00000007 9 exts $t1, $t2, 1, 7 :: rt 0x70 rs 0x9823b6e0, p 0x00000001, lenm1 0x00000007 10 exts $t1, $t2, 1, 7 :: rt [all...] |
/external/vixl/src/a64/ |
H A D | assembler-a64.cc | 479 void Assembler::cbz(const Register& rt, argument 481 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt)); 485 void Assembler::cbz(const Register& rt, argument 487 cbz(rt, UpdateAndGetInstructionOffsetTo(label)); 491 void Assembler::cbnz(const Register& rt, argument 493 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt)); 497 void Assembler::cbnz(const Register& rt, argument 499 cbnz(rt, UpdateAndGetInstructionOffsetT 503 tbz(const Register& rt, unsigned bit_pos, int imm14) argument 511 tbz(const Register& rt, unsigned bit_pos, Label* label) argument 518 tbnz(const Register& rt, unsigned bit_pos, int imm14) argument 526 tbnz(const Register& rt, unsigned bit_pos, Label* label) argument 1024 ldp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& src) argument 1031 stp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& dst) argument 1038 ldpsw(const Register& rt, const Register& rt2, const MemOperand& src) argument 1046 LoadStorePair(const CPURegister& rt, const CPURegister& rt2, const MemOperand& addr, LoadStorePairOp op) argument 1073 ldnp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& src) argument 1081 stnp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& dst) argument 1089 LoadStorePairNonTemporal(const CPURegister& rt, const CPURegister& rt2, const MemOperand& addr, LoadStorePairNonTemporalOp op) argument 1105 ldrb(const Register& rt, const MemOperand& src) argument 1110 strb(const Register& rt, const MemOperand& dst) argument 1115 ldrsb(const Register& rt, const MemOperand& src) argument 1120 ldrh(const Register& rt, const MemOperand& src) argument 1125 strh(const Register& rt, const MemOperand& dst) argument 1130 ldrsh(const Register& rt, const MemOperand& src) argument 1135 ldr(const CPURegister& rt, const MemOperand& src) argument 1140 str(const CPURegister& rt, const MemOperand& src) argument 1145 ldrsw(const Register& rt, const MemOperand& src) argument 1151 ldr(const Register& rt, uint64_t imm) argument 1185 mrs(const Register& rt, SystemRegister sysreg) argument 1191 msr(SystemRegister sysreg, const Register& rt) argument 1838 LoadStore(const CPURegister& rt, const MemOperand& addr, LoadStoreOp op) argument 1900 LoadLiteral(const CPURegister& rt, uint64_t imm, LoadLiteralOp op) argument 2067 LoadOpFor(const CPURegister& rt) argument 2078 LoadPairOpFor(const CPURegister& rt, const CPURegister& rt2) argument 2091 StoreOpFor(const CPURegister& rt) argument 2102 StorePairOpFor(const CPURegister& rt, const CPURegister& rt2) argument 2115 LoadPairNonTemporalOpFor( const CPURegister& rt, const CPURegister& rt2) argument 2128 StorePairNonTemporalOpFor( const CPURegister& rt, const CPURegister& rt2) argument [all...] |
H A D | assembler-a64.h | 703 void cbz(const Register& rt, Label* label); 706 void cbz(const Register& rt, int imm19); 709 void cbnz(const Register& rt, Label* label); 712 void cbnz(const Register& rt, int imm19); 715 void tbz(const Register& rt, unsigned bit_pos, Label* label); 718 void tbz(const Register& rt, unsigned bit_pos, int imm14); 721 void tbnz(const Register& rt, unsigned bit_pos, Label* label); 724 void tbnz(const Register& rt, unsigned bit_pos, int imm14); 1115 void ldr(const CPURegister& rt, const MemOperand& src); 1118 void str(const CPURegister& rt, cons [all...] |
H A D | macro-assembler-a64.cc | 723 void MacroAssembler::LoadStoreMacro(const CPURegister& rt, argument 739 LoadStore(rt, MemOperand(addr.base(), temp), op); 742 LoadStore(rt, MemOperand(addr.base()), op); 747 LoadStore(rt, MemOperand(addr.base()), op); 750 LoadStore(rt, addr, op);
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H A D | macro-assembler-a64.h | 36 V(Ldrb, Register&, rt, LDRB_w) \ 37 V(Strb, Register&, rt, STRB_w) \ 38 V(Ldrsb, Register&, rt, rt.Is64Bits() ? LDRSB_x : LDRSB_w) \ 39 V(Ldrh, Register&, rt, LDRH_w) \ 40 V(Strh, Register&, rt, STRH_w) \ 41 V(Ldrsh, Register&, rt, rt.Is64Bits() ? LDRSH_x : LDRSH_w) \ 42 V(Ldr, CPURegister&, rt, LoadOpFor(rt)) \ 429 Cbnz(const Register& rt, Label* label) argument 434 Cbz(const Register& rt, Label* label) argument 731 Ldnp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& src) argument 737 Ldp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& src) argument 743 Ldpsw(const Register& rt, const Register& rt2, const MemOperand& src) argument 767 Ldr(const Register& rt, uint64_t imm) argument 825 Mrs(const Register& rt, SystemRegister sysreg) argument 830 Msr(SystemRegister sysreg, const Register& rt) argument 965 Stnp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& dst) argument 971 Stp(const CPURegister& rt, const CPURegister& rt2, const MemOperand& dst) argument 995 Tbnz(const Register& rt, unsigned bit_pos, Label* label) argument 1000 Tbz(const Register& rt, unsigned bit_pos, Label* label) argument [all...] |
H A D | simulator-a64.cc | 573 unsigned rt = instr->Rt(); 576 case CBZ_w: take_branch = (wreg(rt) == 0); break; 577 case CBZ_x: take_branch = (xreg(rt) == 0); break; 578 case CBNZ_w: take_branch = (wreg(rt) != 0); break; 579 case CBNZ_x: take_branch = (xreg(rt) != 0); break; 841 unsigned rt = instr->Rt(); local 849 // 'rt' and 'rt2' can only be aliased for stores. 850 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2)); 854 set_wreg(rt, MemoryRead32(address)); 859 set_sreg(rt, MemoryReadFP3 906 unsigned rt = instr->Rt(); local [all...] |
/external/valgrind/main/VEX/priv/ |
H A D | guest_mips_defs.h | 11 mips-valgrind@rt-rk.com 98 extern UInt mips32_dirtyhelper_rdhwr ( UInt rt, UInt rd ); 99 extern ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd );
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H A D | guest_mips_helpers.c | 11 mips-valgrind@rt-rk.com 1079 UInt mips32_dirtyhelper_rdhwr ( UInt rt, UInt rd ) argument 1094 ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd ) argument
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H A D | guest_mips_toIR.c | 11 mips-valgrind@rt-rk.com 500 getIReg(rt), \ 512 mkNarrowTo32(ty, getIReg(rt)), \ 523 putIReg(rd, binop(op, getIReg(rt), mkU8(sa))); 526 putIReg(rd, binop(op, getIReg(rs), getIReg(rt))); 529 putIReg(rt, binop(op, getIReg(rs), mkU32(imm))); 532 putIReg(rt, binop(op, getIReg(rs), mkU64(imm))); 537 mkNarrowTo32(ty, getIReg(rt))), True)); 725 UInt rt = get_rt(cins); local 735 if (opcode == 0x01 && rt 785 UInt rt = get_rt(cins); local 815 UInt rt = get_rt(cins); local 2376 UInt opcode, rs, rt, rd, sa, function, ac, ac_mfhilo, rddsp_mask, local 11688 UInt opcode, cins, rs, rt, rd, sa, ft, fs, fd, fmt, tf, nd, function, local [all...] |
H A D | host_mips_defs.c | 11 mips-valgrind@rt-rk.com 2447 rt - 5 bits 2450 static UChar *mkFormI(UChar * p, UInt opc, UInt rs, UInt rt, UInt imm) argument 2455 vassert(rt < 0x20); 2457 theInstr = ((opc << 26) | (rs << 21) | (rt << 16) | (imm)); 2463 rt - 5 bits 2468 static UChar *mkFormR(UChar * p, UInt opc, UInt rs, UInt rt, UInt rd, UInt sa, argument 2476 vassert(rt < 0x20); 2480 theInstr = ((opc << 26) | (rs << 21) | (rt << 16) | (rd << 11) | (sa << 6) | 4026 UInt rt, f local [all...] |
/external/valgrind/main/coregrind/m_gdbserver/ |
H A D | valgrind-low-mips32.c | 172 UInt op, rs, rt; local 178 rt = itype_rt (inst); 183 || (rs == 9 && (rt & 0x2) == 0) 185 || (rs == 10 && (rt & 0x2) == 0)))); 196 rt = itype_rt (inst); /* branch condition */ 197 return ((rt & 0xc) == 0 200 || ((rt & 0x1e) == 0x1c && rs == 0));
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H A D | valgrind-low-mips64.c | 173 UInt op, rs, rt; local 179 rt = itype_rt (inst); 184 || (rs == 9 && (rt & 0x2) == 0) 186 || (rs == 10 && (rt & 0x2) == 0)))); 197 rt = itype_rt (inst); /* branch condition */ 198 return ((rt & 0xc) == 0 201 || ((rt & 0x1e) == 0x1c && rs == 0));
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/external/valgrind/main/none/tests/mips32/ |
H A D | MoveIns.stdout.exp | 2 mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266 3 mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666 4 mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000 5 mfc1 $t4, $f3 :: fs 0.000000, rt 0x0 6 mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000 7 mfc1 $t6, $f5 :: fs 0.000000, rt 0x0 8 mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b 9 mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a 10 mfc1 $v1, $f8 :: fs nan, rt 0xffffffff 11 mfc1 $s0, $f9 :: fs nan, rt [all...] |
H A D | mips32_dspr2.stdout.exp | 2 absq_s.qb $t0, $t1 :: rd 0x00000000 rt 0x00000000 DSPControl 0x0 3 absq_s.qb $t2, $t3 :: rd 0x0000027a rt 0x00000286 DSPControl 0x0 4 absq_s.qb $t4, $t1 :: rd 0x06442435 rt 0xfabc2435 DSPControl 0x0 5 absq_s.qb $t6, $t7 :: rd 0x73467f44 rt 0x734680bc DSPControl 0x100000 6 absq_s.qb $t5, $t3 :: rd 0x7f000000 rt 0x80000000 DSPControl 0x100000 7 absq_s.qb $t2, $t4 :: rd 0x01010101 rt 0xffffffff DSPControl 0x0 8 absq_s.qb $t0, $t8 :: rd 0x010c5f01 rt 0xfff45fff DSPControl 0x0 9 absq_s.qb $t4, $t4 :: rd 0x00000555 rt 0x00000555 DSPControl 0x0 10 absq_s.qb $t0, $t1 :: rd 0x23534870 rt 0x23534870 DSPControl 0x0 11 absq_s.qb $t2, $t3 :: rd 0x05555314 rt [all...] |
/external/tremolo/Tremolo/ |
H A D | framing.c | 69 ogg_reference *rt; local 74 rt=bs->unused_references; 83 while(rt){ 84 ogg_reference *r=rt; 85 rt=r->next;
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/external/strace/ |
H A D | time.c | 742 print_rtc(struct tcb *tcp, const struct rtc_time *rt) argument 746 rt->tm_sec, rt->tm_min, rt->tm_hour, 747 rt->tm_mday, rt->tm_mon, rt->tm_year); 750 rt->tm_wday, rt->tm_yday, rt 762 struct rtc_time rt; local 774 struct rtc_time rt; local [all...] |
/external/stressapptest/ |
H A D | configure | 5171 for ac_lib in '' rt; do
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/external/speex/libspeex/ |
H A D | math_approx.h | 145 spx_word32_t rt; local 148 rt = ADD16(C0, MULT16_16_Q14(x, ADD16(C1, MULT16_16_Q14(x, ADD16(C2, MULT16_16_Q14(x, (C3))))))); 149 rt = VSHR32(rt,7-k); 150 return rt;
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/external/sonivox/jet_tools/JetCreator/ |
H A D | img_splash.py | 931 \x109\rt\xb1A/~\x85a\xf3L\xb1\x8f\xc1\xb7\x9fI\'\x87\xa2\x9e\xeawt\xee\xcdo\
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/external/skia/src/gpu/ |
H A D | GrClipMaskManager.cpp | 123 GrRenderTarget* rt = drawState->getRenderTarget(); local 159 if (rt->isMultisampled()) { 226 const GrRenderTarget* rt = drawState->getRenderTarget(); local 228 SkASSERT(NULL != rt); 233 SkIRect clipSpaceRTIBounds = SkIRect::MakeWH(rt->width(), rt->height()); 285 if (0 == rt->numSamples() && requiresAA) { 704 GrRenderTarget* rt = drawState->getRenderTarget(); local 705 SkASSERT(NULL != rt); 708 GrStencilBuffer* stencilBuffer = rt [all...] |
H A D | GrDrawState.cpp | 29 void GrDrawState::setFromPaint(const GrPaint& paint, const SkMatrix& vm, GrRenderTarget* rt) { argument 43 this->setRenderTarget(rt);
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