Searched refs:szB (Results 1 - 25 of 63) sorted by last modified time

123

/external/valgrind/main/tests/
H A Dmalloc.h14 static void* memalign16(size_t szB) argument
19 x = malloc(szB);
21 x = memalign(16, szB);
/external/valgrind/main/VEX/priv/
H A Dguest_amd64_toIR.c2281 Int szB = vbi->guest_stack_redzone_size; local
2282 vassert(szB >= 0);
2287 vassert(szB == 128);
2292 if (szB > 0)
2294 binop(Iop_Sub64, mkexpr(new_rsp), mkU64(szB)),
2295 szB,
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H A Dguest_arm64_toIR.c948 static IRType preferredVectorSubTypeFromSize ( UInt szB )
950 switch (szB) {
3092 static void gen_narrowing_store ( UInt szB, IRTemp addr, IRExpr* dataE ) argument
3095 switch (szB) {
3116 static IRTemp gen_zwidening_load ( UInt szB, IRTemp addr ) argument
3120 switch (szB) {
3164 UInt szB = 1 << szLg2; local
3166 UInt offs = INSN(21,10) * szB;
3174 putIReg64orZR(tt, mkexpr(gen_zwidening_load(szB, ta)));
3176 gen_narrowing_store(szB, t
3215 UInt szB = 1 << szLg2; local
3534 UInt szB = 1 << szLg2; local
3768 UInt szB = 4 << szSlg2; /* szB is the per-register size */ local
4124 UInt szB = 4 << INSN(31,30); local
4459 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */ local
4511 UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */ local
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H A Dguest_ppc_toIR.c1662 Int szB = vbi->guest_stack_redzone_size; local
1664 vassert(szB >= 0);
1665 if (szB > 0) {
1669 binop(Iop_Sub64, getIReg(1), mkU64(szB)),
1670 szB,
1676 binop(Iop_Sub32, getIReg(1), mkU32(szB)),
1677 szB,
H A Dhost_amd64_defs.c821 AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB )
827 i->Ain.A87PushPop.szB = szB;
828 vassert(szB == 8 || szB == 4);
1184 i->Ain.A87PushPop.szB == 4 ? 's' : 'l');
3050 vassert(i->Ain.A87PushPop.szB == 8 || i->Ain.A87PushPop.szB == 4);
3055 *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD;
3061 *p++ = i->Ain.A87PushPop.szB
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H A Dhost_amd64_defs.h568 UChar szB; /* 4 or 8 */ member in struct:__anon31681::__anon31682::__anon31708
724 extern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB );
H A Dhost_arm64_defs.c239 ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB ) {
244 am->ARM64am.RI12.szB = szB;
246 switch (szB) {
269 vex_printf("%u(", (UInt)am->ARM64am.RI12.szB
1492 ARM64Instr* ARM64Instr_LdrEX ( Int szB ) {
1495 i->ARM64in.LdrEX.szB = szB;
1496 vassert(szB == 8 || szB
1828 ARM64Instr_VMov( UInt szB, HReg dst, HReg src ) argument
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H A Dhost_arm64_defs.h123 ARM64am_RI12, /* reg + uimm12 * szB (iow, scaled by access size) */
139 UChar szB; /* 1, 2, 4, 8 (16 ?) */ member in struct:__anon31732::__anon31733::__anon31735
150 extern ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB );
764 Int szB; /* 1, 2, 4 or 8 */ member in struct:__anon31763::__anon31764::__anon31785
768 Int szB; /* 1, 2, 4 or 8 */ member in struct:__anon31763::__anon31764::__anon31786
1011 UInt szB; // 16=mov qD,qS; 8=mov dD,dS; 4=mov sD,sS member in struct:__anon31763::__anon31764::__anon31809
1057 extern ARM64Instr* ARM64Instr_LdrEX ( Int szB );
1058 extern ARM64Instr* ARM64Instr_StrEX ( Int szB );
1103 extern ARM64Instr* ARM64Instr_VMov ( UInt szB, HReg dst, HReg src );
H A Dhost_arm64_isel.c862 && isValidScale(am->ARM64am.RI12.szB) );
923 ULong szB = 1 << szBbits; local
924 if (0 == (uimm & (szB-1)) /* "uimm is szB-aligned" */
927 return ARM64AMode_RI12(reg, (UInt)(uimm >> szBbits), (UChar)szB);
6737 Int szB = 0; local
6741 case Ity_I8: szB = 1; break;
6742 case Ity_I16: szB = 2; break;
6743 case Ity_I32: szB = 4; break;
6744 case Ity_I64: szB
6758 Int szB = 0; local
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H A Dhost_arm_defs.c1249 ARMInstr* ARMInstr_LdrEX ( Int szB ) {
1252 i->ARMin.LdrEX.szB = szB;
1253 vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1);
1256 ARMInstr* ARMInstr_StrEX ( Int szB ) {
1259 i->ARMin.StrEX.szB = szB;
[all...]
H A Dhost_arm_defs.h749 Int szB; /* 1, 2, 4 or 8 */ member in struct:__anon31854::__anon31855::__anon31872
757 Int szB; /* 1, 2, 4 or 8 */ member in struct:__anon31854::__anon31855::__anon31873
982 extern ARMInstr* ARMInstr_LdrEX ( Int szB );
983 extern ARMInstr* ARMInstr_StrEX ( Int szB );
H A Dhost_arm_isel.c6051 Int szB = 0; local
6055 case Ity_I8: szB = 1; break;
6056 case Ity_I16: szB = 2; break;
6057 case Ity_I32: szB = 4; break;
6061 addInstr(env, ARMInstr_LdrEX(szB));
6091 Int szB = 0; local
6095 case Ity_I8: szB = 1; break;
6096 case Ity_I16: szB = 2; break;
6097 case Ity_I32: szB = 4; break;
6102 addInstr(env, ARMInstr_StrEX(szB));
[all...]
H A Dir_defs.c4495 IRType integerIRTypeOfSize ( Int szB )
4497 switch (szB) {
/external/valgrind/main/VEX/pub/
H A Dlibvex_ir.h247 extern IRType integerIRTypeOfSize ( Int szB );
/external/valgrind/main/cachegrind/
H A Dcg_main.c532 Int szB; member in struct:__anon32356::__anon32357::__anon32360
536 Int szB; member in struct:__anon32356::__anon32357::__anon32361
540 Int szB; member in struct:__anon32356::__anon32357::__anon32362
567 case Ev_Dr: return ev->Ev.Dr.szB;
568 case Ev_Dw: return ev->Ev.Dw.szB;
569 case Ev_Dm: return ev->Ev.Dm.szB;
651 VG_(printf)("Dr %p %d EA=", ev->inode, ev->Ev.Dr.szB);
656 VG_(printf)("Dw %p %d EA=", ev->inode, ev->Ev.Dw.szB);
661 VG_(printf)("Dm %p %d EA=", ev->inode, ev->Ev.Dm.szB);
917 evt->Ev.Dr.szB
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/external/valgrind/main/callgrind/
H A Dmain.c253 Int szB; member in struct:__anon32375::__anon32376::__anon32378
257 Int szB; member in struct:__anon32375::__anon32376::__anon32379
261 Int szB; member in struct:__anon32375::__anon32376::__anon32380
290 case Ev_Dr: return ev->Ev.Dr.szB;
291 case Ev_Dw: return ev->Ev.Dw.szB;
292 case Ev_Dm: return ev->Ev.Dm.szB;
338 ev->inode, ev->inode->instr_offset, ev->Ev.Dr.szB);
344 ev->inode, ev->inode->instr_offset, ev->Ev.Dw.szB);
350 ev->inode, ev->inode->instr_offset, ev->Ev.Dm.szB);
631 evt->Ev.Dr.szB
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/external/valgrind/main/coregrind/
H A Dfixup_macho_loadcmds.c157 Bool is_macho_object_file( const void* buf, SizeT szB )
176 if (szB < sizeof(struct fat_header))
181 if (szB < sizeof(struct mach_header_64))
/external/valgrind/main/coregrind/m_aspacemgr/
H A Daspacemgr-common.c371 Int szB; local
378 szB = VG_STACK_GUARD_SZB
381 sres = VG_(am_mmap_anon_float_valgrind)( szB );
387 aspacem_assert(VG_IS_PAGE_ALIGNED(szB));
423 (ULong)(Addr)stack, szB);
430 (void)ML_(am_do_munmap_NO_NOTIFY)( (Addr)stack, szB );
/external/valgrind/main/coregrind/m_debuginfo/
H A Ddebuginfo.c3495 block.szB = (SizeT)mul.ul;
3514 block.szB = (SizeT)mul.ul;
3761 gb.szB = (SizeT)mul.ul;
H A Dmisc.c45 void* ML_(dinfo_zalloc) ( const HChar* cc, SizeT szB ) {
47 vg_assert(szB > 0);
48 v = VG_(arena_malloc)( VG_AR_DINFO, cc, szB );
50 VG_(memset)(v, 0, szB);
H A Dpriv_image.h164 struct { DiImage* img; DiOffT ioff; DiOffT szB; } member in struct:__anon32415
171 static inline DiSlice mk_DiSlice ( DiImage* img, DiOffT ioff, DiOffT szB ) {
172 return (DiSlice){img, ioff, szB};
H A Dpriv_misc.h42 void* ML_(dinfo_zalloc)( const HChar* cc, SizeT szB );
H A Dpriv_tytypes.h105 Int szB; member in struct:__anon32441::__anon32442::__anon32450
109 Int szB; member in struct:__anon32441::__anon32442::__anon32451
118 UWord szB; member in struct:__anon32441::__anon32442::__anon32453
126 Int szB; member in struct:__anon32441::__anon32442::__anon32454
H A Dreaddwarf.c1174 if (escn_debug_info.szB < 4) {
1182 escn_debug_info.szB );
1237 escn_debug_line.szB, ui.stmt_list, str_name );
1245 escn_debug_line.szB - ui.stmt_list
3747 DiOffT frame_size = escn_frame.szB;
3775 VG_(printf)("CFI info: szB %lld, _avma %#lx\n",
3776 escn_frame.szB, frame_avma );
H A Dreaddwarf3.c208 return c->sli_next >= c->sli.ioff + c->sli.szB;
222 return c->sli.ioff + c->sli.szB - c->sli_next;
239 if (c->sli_next + sizeof(UChar) > c->sli.ioff + c->sli.szB) {
251 if (c->sli_next + sizeof(UShort) > c->sli.ioff + c->sli.szB) {
263 if (c->sli_next + sizeof(UInt) > c->sli.ioff + c->sli.szB) {
275 if (c->sli_next + sizeof(ULong) > c->sli.ioff + c->sli.szB) {
494 /* The use of escn_debug_{info,types}.szB seems safe to me even if
496 sections were not found), because DiSlice_INVALID.szB is always
499 if (die >= cc->escn_debug_info.szB) {
500 if (die >= cc->escn_debug_info.szB
1079 Long szB; // 1, 2, 4, 8 or non-positive values only. member in struct:__anon32474
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