/system/core/libpixelflinger/codeflinger/ |
H A D | blending.cpp | 138 MOV(AL, 0, temp.reg, reg_imm(temp.reg, LSR, temp.l)); 148 MOV(AL, 0, fragment.reg, reg_imm(temp.reg, LSR, temp.l)); 331 ADD(AL, 0, factor.reg, fb.reg, reg_imm(fb.reg, LSR, fb.s-1)); 337 reg_imm(fragment.reg, LSR, fragment.s-1)); 343 reg_imm(src_alpha.reg, LSR, src_alpha.s-1)); 350 reg_imm(factor.reg, LSR, factor.s-1)); 371 MOV(AL, 0, factor.reg, reg_imm(factor.reg, LSR, factor.s-8)); 447 if (shift>0) RSB(AL, 0, diff.reg, fb.reg, reg_imm(fragment.reg, LSR, shift)); 465 if (shift>0) SUB(AL, 0, diff.reg, fb.reg, reg_imm(fragment.reg, LSR, shift)); 544 MOV(AL, 0, d.reg, reg_imm(vreg, LSR, vshif [all...] |
H A D | load_store.cpp | 125 MOV(AL, 0, d.reg, reg_imm(s, LSR, l)); // component = packed >> l; 149 MOV(AL, 0, d.reg, reg_imm(s, LSR, l)); // component = packed >> l; 227 ORR(AL, 0, d, d, reg_imm(d, LSR, sbits)); 344 MOV(AL, 0, ireg, reg_imm(s.reg, LSR, sl)); 350 SUB(AL, 0, ireg, s.reg, reg_imm(s.reg, LSR, dbits)); 352 if (shift>0) ADD(AL, 0, ireg, ireg, reg_imm(dither.reg, LSR, shift)); 361 MOV(AL, 0, ireg, reg_imm(s.reg, LSR, shift)); 369 MOV(AL, 0, d.reg, reg_imm(s.reg, LSR, shift)); 371 ORR(AL, 0, d.reg, d.reg, reg_imm(s.reg, LSR, shift)); 378 MOV(AL, 0, d.reg, reg_imm(s.reg, LSR, shif [all...] |
H A D | texturing.cpp | 102 MOV(AL, 0, end, reg_imm(parts.count.reg, LSR, 16)); 166 reg_imm(parts.iterated.reg, LSR, 16)); 839 MOV(AL, 0, u, reg_imm(u, LSR, adjust)); 854 MOV(AL, 0, u, reg_imm(u, LSR, adjust)); 868 MOV(AL, 0, u, reg_imm(u, LSR, adjust)); 937 MOV(AL, 0, u, reg_imm(u, LSR, adjust)); 954 MOV(AL, 0, u, reg_imm(u, LSR, adjust)); 972 MOV(AL, 0, u, reg_imm(u, LSR, adjust)); 1028 MOV(AL, 0, u, reg_imm(u, LSR, adjust)); 1031 AND(AL, 0, temp, mask, reg_imm(pixel, LSR, [all...] |
H A D | GGLAssembler.cpp | 433 ADD(AL, 0, Rs, Rs, reg_imm(parts.count.reg, LSR, 16)); 556 MOV(AL, 0, fragment.reg, reg_imm(incoming.reg, LSR, incoming.l)); 576 reg_imm(mAlphaSource.reg, LSR, shift)); 585 reg_imm(fragment.reg, LSR, shift)); 705 if (shift) CMP(AL, fragment.reg, reg_imm(ref, LSR, shift)); 769 ADDR_SUB(AL, 0, zbase, zbase, reg_imm(parts.count.reg, LSR, 15)); 774 CMP(AL, depth, reg_imm(z, LSR, 16)); 782 MOV(AL, 0, depth, reg_imm(z, LSR, 16));
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H A D | Arm64Assembler.cpp | 157 "LSL", "LSR", "ASR", "ROR" 504 if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_type == LSR) 507 LSR, mAddrMode.reg_imm_shift);
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H A D | MIPSAssembler.cpp | 398 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break; 509 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break; 541 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
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H A D | ARMAssemblerInterface.h | 43 LSL, LSR, ASR, ROR enumerator in enum:android::ARMAssemblerInterface::__anon165
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