compiler_enums.h revision d65c51a556e6649db4e18bd083c8fec37607a442 
1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_COMPILER_ENUMS_H_
18#define ART_COMPILER_DEX_COMPILER_ENUMS_H_
19
20#include "dex_instruction.h"
21
22namespace art {
23
24enum RegisterClass {
25  kCoreReg,
26  kFPReg,
27  kAnyReg,
28};
29
30enum BitsUsed {
31  kSize32Bits,
32  kSize64Bits,
33  kSize128Bits,
34  kSize256Bits,
35  kSize512Bits,
36  kSize1024Bits,
37};
38
39enum SpecialTargetRegister {
40  kSelf,            // Thread pointer.
41  kSuspend,         // Used to reduce suspend checks for some targets.
42  kLr,
43  kPc,
44  kSp,
45  kArg0,
46  kArg1,
47  kArg2,
48  kArg3,
49  kFArg0,
50  kFArg1,
51  kFArg2,
52  kFArg3,
53  kRet0,
54  kRet1,
55  kInvokeTgt,
56  kHiddenArg,
57  kHiddenFpArg,
58  kCount
59};
60
61enum RegLocationType {
62  kLocDalvikFrame = 0,  // Normal Dalvik register
63  kLocPhysReg,
64  kLocCompilerTemp,
65  kLocInvalid
66};
67
68enum BBType {
69  kNullBlock,
70  kEntryBlock,
71  kDalvikByteCode,
72  kExitBlock,
73  kExceptionHandling,
74  kDead,
75};
76
77/*
78 * Def/Use encoding in 64-bit use_mask/def_mask.  Low positions used for target-specific
79 * registers (and typically use the register number as the position).  High positions
80 * reserved for common and abstract resources.
81 */
82
83enum ResourceEncodingPos {
84  kMustNotAlias = 63,
85  kHeapRef = 62,          // Default memory reference type.
86  kLiteral = 61,          // Literal pool memory reference.
87  kDalvikReg = 60,        // Dalvik v_reg memory reference.
88  kFPStatus = 59,
89  kCCode = 58,
90  kLowestCommonResource = kCCode
91};
92
93// Shared pseudo opcodes - must be < 0.
94enum LIRPseudoOpcode {
95  kPseudoExportedPC = -16,
96  kPseudoSafepointPC = -15,
97  kPseudoIntrinsicRetry = -14,
98  kPseudoSuspendTarget = -13,
99  kPseudoThrowTarget = -12,
100  kPseudoCaseLabel = -11,
101  kPseudoMethodEntry = -10,
102  kPseudoMethodExit = -9,
103  kPseudoBarrier = -8,
104  kPseudoEntryBlock = -7,
105  kPseudoExitBlock = -6,
106  kPseudoTargetLabel = -5,
107  kPseudoDalvikByteCodeBoundary = -4,
108  kPseudoPseudoAlign4 = -3,
109  kPseudoEHBlockLabel = -2,
110  kPseudoNormalBlockLabel = -1,
111};
112
113enum ExtendedMIROpcode {
114  kMirOpFirst = kNumPackedOpcodes,
115  kMirOpPhi = kMirOpFirst,
116  kMirOpCopy,
117  kMirOpFusedCmplFloat,
118  kMirOpFusedCmpgFloat,
119  kMirOpFusedCmplDouble,
120  kMirOpFusedCmpgDouble,
121  kMirOpFusedCmpLong,
122  kMirOpNop,
123  kMirOpNullCheck,
124  kMirOpRangeCheck,
125  kMirOpDivZeroCheck,
126  kMirOpCheck,
127  kMirOpCheckPart2,
128  kMirOpSelect,
129
130  // Vector opcodes:
131  // TypeSize is an encoded field giving the element type and the vector size.
132  // It is encoded as OpSize << 16 | (number of bits in vector)
133  //
134  // Destination and source are integers that will be interpreted by the
135  // backend that supports Vector operations.  Backends are permitted to support only
136  // certain vector register sizes.
137  //
138  // At this point, only two operand instructions are supported.  Three operand instructions
139  // could be supported by using a bit in TypeSize and arg[0] where needed.
140
141  // @brief MIR to move constant data to a vector register
142  // vA: number of bits in register
143  // vB: destination
144  // args[0]~args[3]: up to 128 bits of data for initialization
145  kMirOpConstVector,
146
147  // @brief MIR to move a vectorized register to another
148  // vA: TypeSize
149  // vB: destination
150  // vC: source
151  kMirOpMoveVector,
152
153  // @brief Packed multiply of units in two vector registers: vB = vB .* vC using vA to know the type of the vector.
154  // vA: TypeSize
155  // vB: destination and source
156  // vC: source
157  kMirOpPackedMultiply,
158
159  // @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector.
160  // vA: TypeSize
161  // vB: destination and source
162  // vC: source
163  kMirOpPackedAddition,
164
165  // @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector.
166  // vA: TypeSize
167  // vB: destination and source
168  // vC: source
169  kMirOpPackedSubtract,
170
171  // @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector.
172  // vA: TypeSize
173  // vB: destination and source
174  // vC: immediate
175  kMirOpPackedShiftLeft,
176
177  // @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector.
178  // vA: TypeSize
179  // vB: destination and source
180  // vC: immediate
181  kMirOpPackedSignedShiftRight,
182
183  // @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector.
184  // vA: TypeSize
185  // vB: destination and source
186  // vC: immediate
187  kMirOpPackedUnsignedShiftRight,
188
189  // @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector.
190  // vA: TypeSize
191  // vB: destination and source
192  // vC: source
193  kMirOpPackedAnd,
194
195  // @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector.
196  // vA: TypeSize
197  // vB: destination and source
198  // vC: source
199  kMirOpPackedOr,
200
201  // @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector.
202  // vA: TypeSize
203  // vB: destination and source
204  // vC: source
205  kMirOpPackedXor,
206
207  // @brief Reduce a 128-bit packed element into a single VR by taking lower bits
208  // @details Instruction does a horizontal addition of the packed elements and then adds it to VR
209  // vA: TypeSize
210  // vB: destination and source VR (not vector register)
211  // vC: source (vector register)
212  kMirOpPackedAddReduce,
213
214  // @brief Extract a packed element into a single VR.
215  // vA: TypeSize
216  // vB: destination VR (not vector register)
217  // vC: source (vector register)
218  // arg[0]: The index to use for extraction from vector register (which packed element)
219  kMirOpPackedReduce,
220
221  // @brief Create a vector value, with all TypeSize values equal to vC
222  // vA: TypeSize
223  // vB: destination vector register
224  // vC: source VR (not vector register)
225  kMirOpPackedSet,
226
227  kMirOpLast,
228};
229
230enum MIROptimizationFlagPositions {
231  kMIRIgnoreNullCheck = 0,
232  kMIRNullCheckOnly,
233  kMIRIgnoreRangeCheck,
234  kMIRRangeCheckOnly,
235  kMIRIgnoreClInitCheck,
236  kMIRInlined,                        // Invoke is inlined (ie dead).
237  kMIRInlinedPred,                    // Invoke is inlined via prediction.
238  kMIRCallee,                         // Instruction is inlined from callee.
239  kMIRIgnoreSuspendCheck,
240  kMIRDup,
241  kMIRMark,                           // Temporary node mark.
242  kMIRLastMIRFlag,
243};
244
245// For successor_block_list.
246enum BlockListType {
247  kNotUsed = 0,
248  kCatch,
249  kPackedSwitch,
250  kSparseSwitch,
251};
252
253enum AssemblerStatus {
254  kSuccess,
255  kRetryAll,
256};
257
258enum OpSize {
259  kWord,            // Natural word size of target (32/64).
260  k32,
261  k64,
262  kReference,       // Object reference; compressed on 64-bit targets.
263  kSingle,
264  kDouble,
265  kUnsignedHalf,
266  kSignedHalf,
267  kUnsignedByte,
268  kSignedByte,
269};
270
271std::ostream& operator<<(std::ostream& os, const OpSize& kind);
272
273enum OpKind {
274  kOpMov,
275  kOpCmov,
276  kOpMvn,
277  kOpCmp,
278  kOpLsl,
279  kOpLsr,
280  kOpAsr,
281  kOpRor,
282  kOpNot,
283  kOpAnd,
284  kOpOr,
285  kOpXor,
286  kOpNeg,
287  kOpAdd,
288  kOpAdc,
289  kOpSub,
290  kOpSbc,
291  kOpRsub,
292  kOpMul,
293  kOpDiv,
294  kOpRem,
295  kOpBic,
296  kOpCmn,
297  kOpTst,
298  kOpRev,
299  kOpRevsh,
300  kOpBkpt,
301  kOpBlx,
302  kOpPush,
303  kOpPop,
304  kOp2Char,
305  kOp2Short,
306  kOp2Byte,
307  kOpCondBr,
308  kOpUncondBr,
309  kOpBx,
310  kOpInvalid,
311};
312
313enum MoveType {
314  kMov8GP,      // Move 8-bit general purpose register.
315  kMov16GP,     // Move 16-bit general purpose register.
316  kMov32GP,     // Move 32-bit general purpose register.
317  kMov64GP,     // Move 64-bit general purpose register.
318  kMov32FP,     // Move 32-bit FP register.
319  kMov64FP,     // Move 64-bit FP register.
320  kMovLo64FP,   // Move low 32-bits of 64-bit FP register.
321  kMovHi64FP,   // Move high 32-bits of 64-bit FP register.
322  kMovU128FP,   // Move 128-bit FP register to/from possibly unaligned region.
323  kMov128FP = kMovU128FP,
324  kMovA128FP,   // Move 128-bit FP register to/from region surely aligned to 16-bytes.
325  kMovLo128FP,  // Move low 64-bits of 128-bit FP register.
326  kMovHi128FP,  // Move high 64-bits of 128-bit FP register.
327};
328
329std::ostream& operator<<(std::ostream& os, const OpKind& kind);
330
331enum ConditionCode {
332  kCondEq,  // equal
333  kCondNe,  // not equal
334  kCondCs,  // carry set
335  kCondCc,  // carry clear
336  kCondUlt,  // unsigned less than
337  kCondUge,  // unsigned greater than or same
338  kCondMi,  // minus
339  kCondPl,  // plus, positive or zero
340  kCondVs,  // overflow
341  kCondVc,  // no overflow
342  kCondHi,  // unsigned greater than
343  kCondLs,  // unsigned lower or same
344  kCondGe,  // signed greater than or equal
345  kCondLt,  // signed less than
346  kCondGt,  // signed greater than
347  kCondLe,  // signed less than or equal
348  kCondAl,  // always
349  kCondNv,  // never
350};
351
352std::ostream& operator<<(std::ostream& os, const ConditionCode& kind);
353
354// Target specific condition encodings
355enum ArmConditionCode {
356  kArmCondEq = 0x0,  // 0000
357  kArmCondNe = 0x1,  // 0001
358  kArmCondCs = 0x2,  // 0010
359  kArmCondCc = 0x3,  // 0011
360  kArmCondMi = 0x4,  // 0100
361  kArmCondPl = 0x5,  // 0101
362  kArmCondVs = 0x6,  // 0110
363  kArmCondVc = 0x7,  // 0111
364  kArmCondHi = 0x8,  // 1000
365  kArmCondLs = 0x9,  // 1001
366  kArmCondGe = 0xa,  // 1010
367  kArmCondLt = 0xb,  // 1011
368  kArmCondGt = 0xc,  // 1100
369  kArmCondLe = 0xd,  // 1101
370  kArmCondAl = 0xe,  // 1110
371  kArmCondNv = 0xf,  // 1111
372};
373
374std::ostream& operator<<(std::ostream& os, const ArmConditionCode& kind);
375
376enum X86ConditionCode {
377  kX86CondO   = 0x0,    // overflow
378  kX86CondNo  = 0x1,    // not overflow
379
380  kX86CondB   = 0x2,    // below
381  kX86CondNae = kX86CondB,  // not-above-equal
382  kX86CondC   = kX86CondB,  // carry
383
384  kX86CondNb  = 0x3,    // not-below
385  kX86CondAe  = kX86CondNb,  // above-equal
386  kX86CondNc  = kX86CondNb,  // not-carry
387
388  kX86CondZ   = 0x4,    // zero
389  kX86CondEq  = kX86CondZ,  // equal
390
391  kX86CondNz  = 0x5,    // not-zero
392  kX86CondNe  = kX86CondNz,  // not-equal
393
394  kX86CondBe  = 0x6,    // below-equal
395  kX86CondNa  = kX86CondBe,  // not-above
396
397  kX86CondNbe = 0x7,    // not-below-equal
398  kX86CondA   = kX86CondNbe,  // above
399
400  kX86CondS   = 0x8,    // sign
401  kX86CondNs  = 0x9,    // not-sign
402
403  kX86CondP   = 0xa,    // 8-bit parity even
404  kX86CondPE  = kX86CondP,
405
406  kX86CondNp  = 0xb,    // 8-bit parity odd
407  kX86CondPo  = kX86CondNp,
408
409  kX86CondL   = 0xc,    // less-than
410  kX86CondNge = kX86CondL,  // not-greater-equal
411
412  kX86CondNl  = 0xd,    // not-less-than
413  kX86CondGe  = kX86CondNl,  // not-greater-equal
414
415  kX86CondLe  = 0xe,    // less-than-equal
416  kX86CondNg  = kX86CondLe,  // not-greater
417
418  kX86CondNle = 0xf,    // not-less-than
419  kX86CondG   = kX86CondNle,  // greater
420};
421
422std::ostream& operator<<(std::ostream& os, const X86ConditionCode& kind);
423
424enum ThrowKind {
425  kThrowNoSuchMethod,
426};
427
428enum DividePattern {
429  DivideNone,
430  Divide3,
431  Divide5,
432  Divide7,
433};
434
435std::ostream& operator<<(std::ostream& os, const DividePattern& pattern);
436
437/**
438 * @brief Memory barrier types (see "The JSR-133 Cookbook for Compiler Writers").
439 * @details Without context sensitive analysis, the most conservative set of barriers
440 * must be issued to ensure the Java Memory Model. Thus the recipe is as follows:
441 * -# Use StoreStore barrier before volatile store.
442 * -# Use StoreLoad barrier after volatile store.
443 * -# Use LoadLoad and LoadStore barrier after each volatile load.
444 * -# Use StoreStore barrier after all stores but before return from any constructor whose
445 * class has final fields.
446 */
447enum MemBarrierKind {
448  kLoadStore,
449  kLoadLoad,
450  kStoreStore,
451  kStoreLoad
452};
453
454std::ostream& operator<<(std::ostream& os, const MemBarrierKind& kind);
455
456enum OpFeatureFlags {
457  kIsBranch = 0,
458  kNoOperand,
459  kIsUnaryOp,
460  kIsBinaryOp,
461  kIsTertiaryOp,
462  kIsQuadOp,
463  kIsQuinOp,
464  kIsSextupleOp,
465  kIsIT,
466  kMemLoad,
467  kMemStore,
468  kPCRelFixup,  // x86 FIXME: add NEEDS_FIXUP to instruction attributes.
469  kRegDef0,
470  kRegDef1,
471  kRegDef2,
472  kRegDefA,
473  kRegDefD,
474  kRegDefFPCSList0,
475  kRegDefFPCSList2,
476  kRegDefList0,
477  kRegDefList1,
478  kRegDefList2,
479  kRegDefLR,
480  kRegDefSP,
481  kRegUse0,
482  kRegUse1,
483  kRegUse2,
484  kRegUse3,
485  kRegUse4,
486  kRegUseA,
487  kRegUseC,
488  kRegUseD,
489  kRegUseB,
490  kRegUseFPCSList0,
491  kRegUseFPCSList2,
492  kRegUseList0,
493  kRegUseList1,
494  kRegUseLR,
495  kRegUsePC,
496  kRegUseSP,
497  kSetsCCodes,
498  kUsesCCodes,
499  kUseFpStack,
500  kUseHi,
501  kUseLo,
502  kDefHi,
503  kDefLo
504};
505
506enum SelectInstructionKind {
507  kSelectNone,
508  kSelectConst,
509  kSelectMove,
510  kSelectGoto
511};
512
513std::ostream& operator<<(std::ostream& os, const SelectInstructionKind& kind);
514
515// LIR fixup kinds for Arm
516enum FixupKind {
517  kFixupNone,
518  kFixupLabel,       // For labels we just adjust the offset.
519  kFixupLoad,        // Mostly for immediates.
520  kFixupVLoad,       // FP load which *may* be pc-relative.
521  kFixupCBxZ,        // Cbz, Cbnz.
522  kFixupPushPop,     // Not really pc relative, but changes size based on args.
523  kFixupCondBranch,  // Conditional branch
524  kFixupT1Branch,    // Thumb1 Unconditional branch
525  kFixupT2Branch,    // Thumb2 Unconditional branch
526  kFixupBlx1,        // Blx1 (start of Blx1/Blx2 pair).
527  kFixupBl1,         // Bl1 (start of Bl1/Bl2 pair).
528  kFixupAdr,         // Adr.
529  kFixupMovImmLST,   // kThumb2MovImm16LST.
530  kFixupMovImmHST,   // kThumb2MovImm16HST.
531  kFixupAlign4,      // Align to 4-byte boundary.
532};
533
534std::ostream& operator<<(std::ostream& os, const FixupKind& kind);
535
536}  // namespace art
537
538#endif  // ART_COMPILER_DEX_COMPILER_ENUMS_H_
539