mir_graph.h revision 3aa57730e2aec451bb836918d936c6862598d8d6
1/* 2 * Copyright (C) 2013 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_MIR_GRAPH_H_ 18#define ART_COMPILER_DEX_MIR_GRAPH_H_ 19 20#include <stdint.h> 21 22#include "dex_file.h" 23#include "dex_instruction.h" 24#include "compiler_ir.h" 25#include "invoke_type.h" 26#include "mir_field_info.h" 27#include "mir_method_info.h" 28#include "utils/arena_bit_vector.h" 29#include "utils/growable_array.h" 30#include "reg_storage.h" 31 32namespace art { 33 34enum InstructionAnalysisAttributePos { 35 kUninterestingOp = 0, 36 kArithmeticOp, 37 kFPOp, 38 kSingleOp, 39 kDoubleOp, 40 kIntOp, 41 kLongOp, 42 kBranchOp, 43 kInvokeOp, 44 kArrayOp, 45 kHeavyweightOp, 46 kSimpleConstOp, 47 kMoveOp, 48 kSwitch 49}; 50 51#define AN_NONE (1 << kUninterestingOp) 52#define AN_MATH (1 << kArithmeticOp) 53#define AN_FP (1 << kFPOp) 54#define AN_LONG (1 << kLongOp) 55#define AN_INT (1 << kIntOp) 56#define AN_SINGLE (1 << kSingleOp) 57#define AN_DOUBLE (1 << kDoubleOp) 58#define AN_FLOATMATH (1 << kFPOp) 59#define AN_BRANCH (1 << kBranchOp) 60#define AN_INVOKE (1 << kInvokeOp) 61#define AN_ARRAYOP (1 << kArrayOp) 62#define AN_HEAVYWEIGHT (1 << kHeavyweightOp) 63#define AN_SIMPLECONST (1 << kSimpleConstOp) 64#define AN_MOVE (1 << kMoveOp) 65#define AN_SWITCH (1 << kSwitch) 66#define AN_COMPUTATIONAL (AN_MATH | AN_ARRAYOP | AN_MOVE | AN_SIMPLECONST) 67 68enum DataFlowAttributePos { 69 kUA = 0, 70 kUB, 71 kUC, 72 kAWide, 73 kBWide, 74 kCWide, 75 kDA, 76 kIsMove, 77 kSetsConst, 78 kFormat35c, 79 kFormat3rc, 80 kNullCheckSrc0, // Null check of uses[0]. 81 kNullCheckSrc1, // Null check of uses[1]. 82 kNullCheckSrc2, // Null check of uses[2]. 83 kNullCheckOut0, // Null check out outgoing arg0. 84 kDstNonNull, // May assume dst is non-null. 85 kRetNonNull, // May assume retval is non-null. 86 kNullTransferSrc0, // Object copy src[0] -> dst. 87 kNullTransferSrcN, // Phi null check state transfer. 88 kRangeCheckSrc1, // Range check of uses[1]. 89 kRangeCheckSrc2, // Range check of uses[2]. 90 kRangeCheckSrc3, // Range check of uses[3]. 91 kFPA, 92 kFPB, 93 kFPC, 94 kCoreA, 95 kCoreB, 96 kCoreC, 97 kRefA, 98 kRefB, 99 kRefC, 100 kUsesMethodStar, // Implicit use of Method*. 101 kUsesIField, // Accesses an instance field (IGET/IPUT). 102 kUsesSField, // Accesses a static field (SGET/SPUT). 103 kDoLVN, // Worth computing local value numbers. 104}; 105 106#define DF_NOP UINT64_C(0) 107#define DF_UA (UINT64_C(1) << kUA) 108#define DF_UB (UINT64_C(1) << kUB) 109#define DF_UC (UINT64_C(1) << kUC) 110#define DF_A_WIDE (UINT64_C(1) << kAWide) 111#define DF_B_WIDE (UINT64_C(1) << kBWide) 112#define DF_C_WIDE (UINT64_C(1) << kCWide) 113#define DF_DA (UINT64_C(1) << kDA) 114#define DF_IS_MOVE (UINT64_C(1) << kIsMove) 115#define DF_SETS_CONST (UINT64_C(1) << kSetsConst) 116#define DF_FORMAT_35C (UINT64_C(1) << kFormat35c) 117#define DF_FORMAT_3RC (UINT64_C(1) << kFormat3rc) 118#define DF_NULL_CHK_0 (UINT64_C(1) << kNullCheckSrc0) 119#define DF_NULL_CHK_1 (UINT64_C(1) << kNullCheckSrc1) 120#define DF_NULL_CHK_2 (UINT64_C(1) << kNullCheckSrc2) 121#define DF_NULL_CHK_OUT0 (UINT64_C(1) << kNullCheckOut0) 122#define DF_NON_NULL_DST (UINT64_C(1) << kDstNonNull) 123#define DF_NON_NULL_RET (UINT64_C(1) << kRetNonNull) 124#define DF_NULL_TRANSFER_0 (UINT64_C(1) << kNullTransferSrc0) 125#define DF_NULL_TRANSFER_N (UINT64_C(1) << kNullTransferSrcN) 126#define DF_RANGE_CHK_1 (UINT64_C(1) << kRangeCheckSrc1) 127#define DF_RANGE_CHK_2 (UINT64_C(1) << kRangeCheckSrc2) 128#define DF_RANGE_CHK_3 (UINT64_C(1) << kRangeCheckSrc3) 129#define DF_FP_A (UINT64_C(1) << kFPA) 130#define DF_FP_B (UINT64_C(1) << kFPB) 131#define DF_FP_C (UINT64_C(1) << kFPC) 132#define DF_CORE_A (UINT64_C(1) << kCoreA) 133#define DF_CORE_B (UINT64_C(1) << kCoreB) 134#define DF_CORE_C (UINT64_C(1) << kCoreC) 135#define DF_REF_A (UINT64_C(1) << kRefA) 136#define DF_REF_B (UINT64_C(1) << kRefB) 137#define DF_REF_C (UINT64_C(1) << kRefC) 138#define DF_UMS (UINT64_C(1) << kUsesMethodStar) 139#define DF_IFIELD (UINT64_C(1) << kUsesIField) 140#define DF_SFIELD (UINT64_C(1) << kUsesSField) 141#define DF_LVN (UINT64_C(1) << kDoLVN) 142 143#define DF_HAS_USES (DF_UA | DF_UB | DF_UC) 144 145#define DF_HAS_DEFS (DF_DA) 146 147#define DF_HAS_NULL_CHKS (DF_NULL_CHK_0 | \ 148 DF_NULL_CHK_1 | \ 149 DF_NULL_CHK_2 | \ 150 DF_NULL_CHK_OUT0) 151 152#define DF_HAS_RANGE_CHKS (DF_RANGE_CHK_1 | \ 153 DF_RANGE_CHK_2 | \ 154 DF_RANGE_CHK_3) 155 156#define DF_HAS_NR_CHKS (DF_HAS_NULL_CHKS | \ 157 DF_HAS_RANGE_CHKS) 158 159#define DF_A_IS_REG (DF_UA | DF_DA) 160#define DF_B_IS_REG (DF_UB) 161#define DF_C_IS_REG (DF_UC) 162#define DF_IS_GETTER_OR_SETTER (DF_IS_GETTER | DF_IS_SETTER) 163#define DF_USES_FP (DF_FP_A | DF_FP_B | DF_FP_C) 164#define DF_NULL_TRANSFER (DF_NULL_TRANSFER_0 | DF_NULL_TRANSFER_N) 165enum OatMethodAttributes { 166 kIsLeaf, // Method is leaf. 167 kHasLoop, // Method contains simple loop. 168}; 169 170#define METHOD_IS_LEAF (1 << kIsLeaf) 171#define METHOD_HAS_LOOP (1 << kHasLoop) 172 173// Minimum field size to contain Dalvik v_reg number. 174#define VREG_NUM_WIDTH 16 175 176#define INVALID_SREG (-1) 177#define INVALID_VREG (0xFFFFU) 178#define INVALID_OFFSET (0xDEADF00FU) 179 180#define MIR_IGNORE_NULL_CHECK (1 << kMIRIgnoreNullCheck) 181#define MIR_NULL_CHECK_ONLY (1 << kMIRNullCheckOnly) 182#define MIR_IGNORE_RANGE_CHECK (1 << kMIRIgnoreRangeCheck) 183#define MIR_RANGE_CHECK_ONLY (1 << kMIRRangeCheckOnly) 184#define MIR_IGNORE_CLINIT_CHECK (1 << kMIRIgnoreClInitCheck) 185#define MIR_INLINED (1 << kMIRInlined) 186#define MIR_INLINED_PRED (1 << kMIRInlinedPred) 187#define MIR_CALLEE (1 << kMIRCallee) 188#define MIR_IGNORE_SUSPEND_CHECK (1 << kMIRIgnoreSuspendCheck) 189#define MIR_DUP (1 << kMIRDup) 190 191#define BLOCK_NAME_LEN 80 192 193typedef uint16_t BasicBlockId; 194static const BasicBlockId NullBasicBlockId = 0; 195 196/* 197 * In general, vreg/sreg describe Dalvik registers that originated with dx. However, 198 * it is useful to have compiler-generated temporary registers and have them treated 199 * in the same manner as dx-generated virtual registers. This struct records the SSA 200 * name of compiler-introduced temporaries. 201 */ 202struct CompilerTemp { 203 int32_t v_reg; // Virtual register number for temporary. 204 int32_t s_reg_low; // SSA name for low Dalvik word. 205}; 206 207enum CompilerTempType { 208 kCompilerTempVR, // A virtual register temporary. 209 kCompilerTempSpecialMethodPtr, // Temporary that keeps track of current method pointer. 210}; 211 212// When debug option enabled, records effectiveness of null and range check elimination. 213struct Checkstats { 214 int32_t null_checks; 215 int32_t null_checks_eliminated; 216 int32_t range_checks; 217 int32_t range_checks_eliminated; 218}; 219 220// Dataflow attributes of a basic block. 221struct BasicBlockDataFlow { 222 ArenaBitVector* use_v; 223 ArenaBitVector* def_v; 224 ArenaBitVector* live_in_v; 225 ArenaBitVector* phi_v; 226 int32_t* vreg_to_ssa_map; 227 ArenaBitVector* ending_check_v; // For null check and class init check elimination. 228}; 229 230/* 231 * Normalized use/def for a MIR operation using SSA names rather than vregs. Note that 232 * uses/defs retain the Dalvik convention that long operations operate on a pair of 32-bit 233 * vregs. For example, "ADD_LONG v0, v2, v3" would have 2 defs (v0/v1) and 4 uses (v2/v3, v4/v5). 234 * Following SSA renaming, this is the primary struct used by code generators to locate 235 * operand and result registers. This is a somewhat confusing and unhelpful convention that 236 * we may want to revisit in the future. 237 */ 238struct SSARepresentation { 239 int16_t num_uses; 240 int16_t num_defs; 241 int32_t* uses; 242 bool* fp_use; 243 int32_t* defs; 244 bool* fp_def; 245 246 static uint32_t GetStartUseIndex(Instruction::Code opcode); 247}; 248 249/* 250 * The Midlevel Intermediate Representation node, which may be largely considered a 251 * wrapper around a Dalvik byte code. 252 */ 253struct MIR { 254 /* 255 * TODO: remove embedded DecodedInstruction to save space, keeping only opcode. Recover 256 * additional fields on as-needed basis. Question: how to support MIR Pseudo-ops; probably 257 * need to carry aux data pointer. 258 */ 259 struct DecodedInstruction { 260 uint32_t vA; 261 uint32_t vB; 262 uint64_t vB_wide; /* for k51l */ 263 uint32_t vC; 264 uint32_t arg[5]; /* vC/D/E/F/G in invoke or filled-new-array */ 265 Instruction::Code opcode; 266 267 explicit DecodedInstruction():vA(0), vB(0), vB_wide(0), vC(0), opcode(Instruction::NOP) { 268 } 269 } dalvikInsn; 270 271 NarrowDexOffset offset; // Offset of the instruction in code units. 272 uint16_t optimization_flags; 273 int16_t m_unit_index; // From which method was this MIR included 274 BasicBlockId bb; 275 MIR* next; 276 SSARepresentation* ssa_rep; 277 union { 278 // Incoming edges for phi node. 279 BasicBlockId* phi_incoming; 280 // Establish link from check instruction (kMirOpCheck) to the actual throwing instruction. 281 MIR* throw_insn; 282 // Branch condition for fused cmp or select. 283 ConditionCode ccode; 284 // IGET/IPUT lowering info index, points to MIRGraph::ifield_lowering_infos_. Due to limit on 285 // the number of code points (64K) and size of IGET/IPUT insn (2), this will never exceed 32K. 286 uint32_t ifield_lowering_info; 287 // SGET/SPUT lowering info index, points to MIRGraph::sfield_lowering_infos_. Due to limit on 288 // the number of code points (64K) and size of SGET/SPUT insn (2), this will never exceed 32K. 289 uint32_t sfield_lowering_info; 290 // INVOKE data index, points to MIRGraph::method_lowering_infos_. 291 uint32_t method_lowering_info; 292 } meta; 293 294 explicit MIR():offset(0), optimization_flags(0), m_unit_index(0), bb(NullBasicBlockId), 295 next(nullptr), ssa_rep(nullptr) { 296 memset(&meta, 0, sizeof(meta)); 297 } 298 299 uint32_t GetStartUseIndex() const { 300 return SSARepresentation::GetStartUseIndex(dalvikInsn.opcode); 301 } 302 303 MIR* Copy(CompilationUnit *c_unit); 304 MIR* Copy(MIRGraph* mir_Graph); 305 306 static void* operator new(size_t size, ArenaAllocator* arena) { 307 return arena->Alloc(sizeof(MIR), kArenaAllocMIR); 308 } 309 static void operator delete(void* p) {} // Nop. 310}; 311 312struct SuccessorBlockInfo; 313 314struct BasicBlock { 315 BasicBlockId id; 316 BasicBlockId dfs_id; 317 NarrowDexOffset start_offset; // Offset in code units. 318 BasicBlockId fall_through; 319 BasicBlockId taken; 320 BasicBlockId i_dom; // Immediate dominator. 321 uint16_t nesting_depth; 322 BBType block_type:4; 323 BlockListType successor_block_list_type:4; 324 bool visited:1; 325 bool hidden:1; 326 bool catch_entry:1; 327 bool explicit_throw:1; 328 bool conditional_branch:1; 329 bool terminated_by_return:1; // Block ends with a Dalvik return opcode. 330 bool dominates_return:1; // Is a member of return extended basic block. 331 bool use_lvn:1; // Run local value numbering on this block. 332 MIR* first_mir_insn; 333 MIR* last_mir_insn; 334 BasicBlockDataFlow* data_flow_info; 335 ArenaBitVector* dominators; 336 ArenaBitVector* i_dominated; // Set nodes being immediately dominated. 337 ArenaBitVector* dom_frontier; // Dominance frontier. 338 GrowableArray<BasicBlockId>* predecessors; 339 GrowableArray<SuccessorBlockInfo*>* successor_blocks; 340 341 void AppendMIR(MIR* mir); 342 void PrependMIR(MIR* mir); 343 void InsertMIRAfter(MIR* current_mir, MIR* new_mir); 344 void InsertMIRBefore(MIR* current_mir, MIR* new_mir); 345 MIR* FindPreviousMIR(MIR* mir); 346 347 /** 348 * @brief Used to obtain the next MIR that follows unconditionally. 349 * @details The implementation does not guarantee that a MIR does not 350 * follow even if this method returns nullptr. 351 * @param mir_graph the MIRGraph. 352 * @param current The MIR for which to find an unconditional follower. 353 * @return Returns the following MIR if one can be found. 354 */ 355 MIR* GetNextUnconditionalMir(MIRGraph* mir_graph, MIR* current); 356 bool RemoveMIR(MIR* mir); 357}; 358 359/* 360 * The "blocks" field in "successor_block_list" points to an array of elements with the type 361 * "SuccessorBlockInfo". For catch blocks, key is type index for the exception. For swtich 362 * blocks, key is the case value. 363 */ 364struct SuccessorBlockInfo { 365 BasicBlockId block; 366 int key; 367}; 368 369/** 370 * @class ChildBlockIterator 371 * @brief Enable an easy iteration of the children. 372 */ 373class ChildBlockIterator { 374 public: 375 /** 376 * @brief Constructs a child iterator. 377 * @param bb The basic whose children we need to iterate through. 378 * @param mir_graph The MIRGraph used to get the basic block during iteration. 379 */ 380 ChildBlockIterator(BasicBlock* bb, MIRGraph* mir_graph); 381 BasicBlock* Next(); 382 383 private: 384 BasicBlock* basic_block_; 385 MIRGraph* mir_graph_; 386 bool visited_fallthrough_; 387 bool visited_taken_; 388 bool have_successors_; 389 GrowableArray<SuccessorBlockInfo*>::Iterator successor_iter_; 390}; 391 392/* 393 * Whereas a SSA name describes a definition of a Dalvik vreg, the RegLocation describes 394 * the type of an SSA name (and, can also be used by code generators to record where the 395 * value is located (i.e. - physical register, frame, spill, etc.). For each SSA name (SReg) 396 * there is a RegLocation. 397 * A note on SSA names: 398 * o SSA names for Dalvik vRegs v0..vN will be assigned 0..N. These represent the "vN_0" 399 * names. Negative SSA names represent special values not present in the Dalvik byte code. 400 * For example, SSA name -1 represents an invalid SSA name, and SSA name -2 represents the 401 * the Method pointer. SSA names < -2 are reserved for future use. 402 * o The vN_0 names for non-argument Dalvik should in practice never be used (as they would 403 * represent the read of an undefined local variable). The first definition of the 404 * underlying Dalvik vReg will result in a vN_1 name. 405 * 406 * FIXME: The orig_sreg field was added as a workaround for llvm bitcode generation. With 407 * the latest restructuring, we should be able to remove it and rely on s_reg_low throughout. 408 */ 409struct RegLocation { 410 RegLocationType location:3; 411 unsigned wide:1; 412 unsigned defined:1; // Do we know the type? 413 unsigned is_const:1; // Constant, value in mir_graph->constant_values[]. 414 unsigned fp:1; // Floating point? 415 unsigned core:1; // Non-floating point? 416 unsigned ref:1; // Something GC cares about. 417 unsigned high_word:1; // High word of pair? 418 unsigned home:1; // Does this represent the home location? 419 RegStorage reg; // Encoded physical registers. 420 int16_t s_reg_low; // SSA name for low Dalvik word. 421 int16_t orig_sreg; // TODO: remove after Bitcode gen complete 422 // and consolidate usage w/ s_reg_low. 423}; 424 425/* 426 * Collection of information describing an invoke, and the destination of 427 * the subsequent MOVE_RESULT (if applicable). Collected as a unit to enable 428 * more efficient invoke code generation. 429 */ 430struct CallInfo { 431 int num_arg_words; // Note: word count, not arg count. 432 RegLocation* args; // One for each word of arguments. 433 RegLocation result; // Eventual target of MOVE_RESULT. 434 int opt_flags; 435 InvokeType type; 436 uint32_t dex_idx; 437 uint32_t index; // Method idx for invokes, type idx for FilledNewArray. 438 uintptr_t direct_code; 439 uintptr_t direct_method; 440 RegLocation target; // Target of following move_result. 441 bool skip_this; 442 bool is_range; 443 DexOffset offset; // Offset in code units. 444 MIR* mir; 445}; 446 447 448const RegLocation bad_loc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0, 0, RegStorage(), INVALID_SREG, 449 INVALID_SREG}; 450 451class MIRGraph { 452 public: 453 MIRGraph(CompilationUnit* cu, ArenaAllocator* arena); 454 ~MIRGraph(); 455 456 /* 457 * Examine the graph to determine whether it's worthwile to spend the time compiling 458 * this method. 459 */ 460 bool SkipCompilation(); 461 462 /* 463 * Should we skip the compilation of this method based on its name? 464 */ 465 bool SkipCompilation(const std::string& methodname); 466 467 /* 468 * Parse dex method and add MIR at current insert point. Returns id (which is 469 * actually the index of the method in the m_units_ array). 470 */ 471 void InlineMethod(const DexFile::CodeItem* code_item, uint32_t access_flags, 472 InvokeType invoke_type, uint16_t class_def_idx, 473 uint32_t method_idx, jobject class_loader, const DexFile& dex_file); 474 475 /* Find existing block */ 476 BasicBlock* FindBlock(DexOffset code_offset) { 477 return FindBlock(code_offset, false, false, NULL); 478 } 479 480 const uint16_t* GetCurrentInsns() const { 481 return current_code_item_->insns_; 482 } 483 484 const uint16_t* GetInsns(int m_unit_index) const { 485 return m_units_[m_unit_index]->GetCodeItem()->insns_; 486 } 487 488 int GetNumBlocks() const { 489 return num_blocks_; 490 } 491 492 size_t GetNumDalvikInsns() const { 493 return cu_->code_item->insns_size_in_code_units_; 494 } 495 496 ArenaBitVector* GetTryBlockAddr() const { 497 return try_block_addr_; 498 } 499 500 BasicBlock* GetEntryBlock() const { 501 return entry_block_; 502 } 503 504 BasicBlock* GetExitBlock() const { 505 return exit_block_; 506 } 507 508 BasicBlock* GetBasicBlock(int block_id) const { 509 return (block_id == NullBasicBlockId) ? NULL : block_list_.Get(block_id); 510 } 511 512 size_t GetBasicBlockListCount() const { 513 return block_list_.Size(); 514 } 515 516 GrowableArray<BasicBlock*>* GetBlockList() { 517 return &block_list_; 518 } 519 520 GrowableArray<BasicBlockId>* GetDfsOrder() { 521 return dfs_order_; 522 } 523 524 GrowableArray<BasicBlockId>* GetDfsPostOrder() { 525 return dfs_post_order_; 526 } 527 528 GrowableArray<BasicBlockId>* GetDomPostOrder() { 529 return dom_post_order_traversal_; 530 } 531 532 int GetDefCount() const { 533 return def_count_; 534 } 535 536 ArenaAllocator* GetArena() { 537 return arena_; 538 } 539 540 void EnableOpcodeCounting() { 541 opcode_count_ = static_cast<int*>(arena_->Alloc(kNumPackedOpcodes * sizeof(int), 542 kArenaAllocMisc)); 543 } 544 545 void ShowOpcodeStats(); 546 547 DexCompilationUnit* GetCurrentDexCompilationUnit() const { 548 return m_units_[current_method_]; 549 } 550 551 /** 552 * @brief Dump a CFG into a dot file format. 553 * @param dir_prefix the directory the file will be created in. 554 * @param all_blocks does the dumper use all the basic blocks or use the reachable blocks. 555 * @param suffix does the filename require a suffix or not (default = nullptr). 556 */ 557 void DumpCFG(const char* dir_prefix, bool all_blocks, const char* suffix = nullptr); 558 559 bool HasFieldAccess() const { 560 return (merged_df_flags_ & (DF_IFIELD | DF_SFIELD)) != 0u; 561 } 562 563 bool HasStaticFieldAccess() const { 564 return (merged_df_flags_ & DF_SFIELD) != 0u; 565 } 566 567 bool HasInvokes() const { 568 // NOTE: These formats include the rare filled-new-array/range. 569 return (merged_df_flags_ & (DF_FORMAT_35C | DF_FORMAT_3RC)) != 0u; 570 } 571 572 void DoCacheFieldLoweringInfo(); 573 574 const MirIFieldLoweringInfo& GetIFieldLoweringInfo(MIR* mir) const { 575 DCHECK_LT(mir->meta.ifield_lowering_info, ifield_lowering_infos_.Size()); 576 return ifield_lowering_infos_.GetRawStorage()[mir->meta.ifield_lowering_info]; 577 } 578 579 const MirSFieldLoweringInfo& GetSFieldLoweringInfo(MIR* mir) const { 580 DCHECK_LT(mir->meta.sfield_lowering_info, sfield_lowering_infos_.Size()); 581 return sfield_lowering_infos_.GetRawStorage()[mir->meta.sfield_lowering_info]; 582 } 583 584 void DoCacheMethodLoweringInfo(); 585 586 const MirMethodLoweringInfo& GetMethodLoweringInfo(MIR* mir) { 587 DCHECK_LT(mir->meta.method_lowering_info, method_lowering_infos_.Size()); 588 return method_lowering_infos_.GetRawStorage()[mir->meta.method_lowering_info]; 589 } 590 591 void ComputeInlineIFieldLoweringInfo(uint16_t field_idx, MIR* invoke, MIR* iget_or_iput); 592 593 void InitRegLocations(); 594 595 void RemapRegLocations(); 596 597 void DumpRegLocTable(RegLocation* table, int count); 598 599 void BasicBlockOptimization(); 600 601 bool IsConst(int32_t s_reg) const { 602 return is_constant_v_->IsBitSet(s_reg); 603 } 604 605 bool IsConst(RegLocation loc) const { 606 return loc.orig_sreg < 0 ? false : IsConst(loc.orig_sreg); 607 } 608 609 int32_t ConstantValue(RegLocation loc) const { 610 DCHECK(IsConst(loc)); 611 return constant_values_[loc.orig_sreg]; 612 } 613 614 int32_t ConstantValue(int32_t s_reg) const { 615 DCHECK(IsConst(s_reg)); 616 return constant_values_[s_reg]; 617 } 618 619 int64_t ConstantValueWide(RegLocation loc) const { 620 DCHECK(IsConst(loc)); 621 return (static_cast<int64_t>(constant_values_[loc.orig_sreg + 1]) << 32) | 622 Low32Bits(static_cast<int64_t>(constant_values_[loc.orig_sreg])); 623 } 624 625 bool IsConstantNullRef(RegLocation loc) const { 626 return loc.ref && loc.is_const && (ConstantValue(loc) == 0); 627 } 628 629 int GetNumSSARegs() const { 630 return num_ssa_regs_; 631 } 632 633 void SetNumSSARegs(int new_num) { 634 /* 635 * TODO: It's theoretically possible to exceed 32767, though any cases which did 636 * would be filtered out with current settings. When orig_sreg field is removed 637 * from RegLocation, expand s_reg_low to handle all possible cases and remove DCHECK(). 638 */ 639 DCHECK_EQ(new_num, static_cast<int16_t>(new_num)); 640 num_ssa_regs_ = new_num; 641 } 642 643 unsigned int GetNumReachableBlocks() const { 644 return num_reachable_blocks_; 645 } 646 647 int GetUseCount(int vreg) const { 648 return use_counts_.Get(vreg); 649 } 650 651 int GetRawUseCount(int vreg) const { 652 return raw_use_counts_.Get(vreg); 653 } 654 655 int GetSSASubscript(int ssa_reg) const { 656 return ssa_subscripts_->Get(ssa_reg); 657 } 658 659 RegLocation GetRawSrc(MIR* mir, int num) { 660 DCHECK(num < mir->ssa_rep->num_uses); 661 RegLocation res = reg_location_[mir->ssa_rep->uses[num]]; 662 return res; 663 } 664 665 RegLocation GetRawDest(MIR* mir) { 666 DCHECK_GT(mir->ssa_rep->num_defs, 0); 667 RegLocation res = reg_location_[mir->ssa_rep->defs[0]]; 668 return res; 669 } 670 671 RegLocation GetDest(MIR* mir) { 672 RegLocation res = GetRawDest(mir); 673 DCHECK(!res.wide); 674 return res; 675 } 676 677 RegLocation GetSrc(MIR* mir, int num) { 678 RegLocation res = GetRawSrc(mir, num); 679 DCHECK(!res.wide); 680 return res; 681 } 682 683 RegLocation GetDestWide(MIR* mir) { 684 RegLocation res = GetRawDest(mir); 685 DCHECK(res.wide); 686 return res; 687 } 688 689 RegLocation GetSrcWide(MIR* mir, int low) { 690 RegLocation res = GetRawSrc(mir, low); 691 DCHECK(res.wide); 692 return res; 693 } 694 695 RegLocation GetBadLoc() { 696 return bad_loc; 697 } 698 699 int GetMethodSReg() const { 700 return method_sreg_; 701 } 702 703 /** 704 * @brief Used to obtain the number of compiler temporaries being used. 705 * @return Returns the number of compiler temporaries. 706 */ 707 size_t GetNumUsedCompilerTemps() const { 708 size_t total_num_temps = compiler_temps_.Size(); 709 DCHECK_LE(num_non_special_compiler_temps_, total_num_temps); 710 return total_num_temps; 711 } 712 713 /** 714 * @brief Used to obtain the number of non-special compiler temporaries being used. 715 * @return Returns the number of non-special compiler temporaries. 716 */ 717 size_t GetNumNonSpecialCompilerTemps() const { 718 return num_non_special_compiler_temps_; 719 } 720 721 /** 722 * @brief Used to set the total number of available non-special compiler temporaries. 723 * @details Can fail setting the new max if there are more temps being used than the new_max. 724 * @param new_max The new maximum number of non-special compiler temporaries. 725 * @return Returns true if the max was set and false if failed to set. 726 */ 727 bool SetMaxAvailableNonSpecialCompilerTemps(size_t new_max) { 728 if (new_max < GetNumNonSpecialCompilerTemps()) { 729 return false; 730 } else { 731 max_available_non_special_compiler_temps_ = new_max; 732 return true; 733 } 734 } 735 736 /** 737 * @brief Provides the number of non-special compiler temps available. 738 * @details Even if this returns zero, special compiler temps are guaranteed to be available. 739 * @return Returns the number of available temps. 740 */ 741 size_t GetNumAvailableNonSpecialCompilerTemps(); 742 743 /** 744 * @brief Used to obtain an existing compiler temporary. 745 * @param index The index of the temporary which must be strictly less than the 746 * number of temporaries. 747 * @return Returns the temporary that was asked for. 748 */ 749 CompilerTemp* GetCompilerTemp(size_t index) const { 750 return compiler_temps_.Get(index); 751 } 752 753 /** 754 * @brief Used to obtain the maximum number of compiler temporaries that can be requested. 755 * @return Returns the maximum number of compiler temporaries, whether used or not. 756 */ 757 size_t GetMaxPossibleCompilerTemps() const { 758 return max_available_special_compiler_temps_ + max_available_non_special_compiler_temps_; 759 } 760 761 /** 762 * @brief Used to obtain a new unique compiler temporary. 763 * @param ct_type Type of compiler temporary requested. 764 * @param wide Whether we should allocate a wide temporary. 765 * @return Returns the newly created compiler temporary. 766 */ 767 CompilerTemp* GetNewCompilerTemp(CompilerTempType ct_type, bool wide); 768 769 bool MethodIsLeaf() { 770 return attributes_ & METHOD_IS_LEAF; 771 } 772 773 RegLocation GetRegLocation(int index) { 774 DCHECK((index >= 0) && (index < num_ssa_regs_)); 775 return reg_location_[index]; 776 } 777 778 RegLocation GetMethodLoc() { 779 return reg_location_[method_sreg_]; 780 } 781 782 bool IsBackedge(BasicBlock* branch_bb, BasicBlockId target_bb_id) { 783 return ((target_bb_id != NullBasicBlockId) && 784 (GetBasicBlock(target_bb_id)->start_offset <= branch_bb->start_offset)); 785 } 786 787 bool IsBackwardsBranch(BasicBlock* branch_bb) { 788 return IsBackedge(branch_bb, branch_bb->taken) || IsBackedge(branch_bb, branch_bb->fall_through); 789 } 790 791 void CountBranch(DexOffset target_offset) { 792 if (target_offset <= current_offset_) { 793 backward_branches_++; 794 } else { 795 forward_branches_++; 796 } 797 } 798 799 int GetBranchCount() { 800 return backward_branches_ + forward_branches_; 801 } 802 803 bool IsPseudoMirOp(Instruction::Code opcode) { 804 return static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst); 805 } 806 807 bool IsPseudoMirOp(int opcode) { 808 return opcode >= static_cast<int>(kMirOpFirst); 809 } 810 811 // Is this vreg in the in set? 812 bool IsInVReg(int vreg) { 813 return (vreg >= cu_->num_regs); 814 } 815 816 void DumpCheckStats(); 817 MIR* FindMoveResult(BasicBlock* bb, MIR* mir); 818 int SRegToVReg(int ssa_reg) const; 819 void VerifyDataflow(); 820 void CheckForDominanceFrontier(BasicBlock* dom_bb, const BasicBlock* succ_bb); 821 void EliminateNullChecksAndInferTypesStart(); 822 bool EliminateNullChecksAndInferTypes(BasicBlock *bb); 823 void EliminateNullChecksAndInferTypesEnd(); 824 bool EliminateClassInitChecksGate(); 825 bool EliminateClassInitChecks(BasicBlock* bb); 826 void EliminateClassInitChecksEnd(); 827 /* 828 * Type inference handling helpers. Because Dalvik's bytecode is not fully typed, 829 * we have to do some work to figure out the sreg type. For some operations it is 830 * clear based on the opcode (i.e. ADD_FLOAT v0, v1, v2), but for others (MOVE), we 831 * may never know the "real" type. 832 * 833 * We perform the type inference operation by using an iterative walk over 834 * the graph, propagating types "defined" by typed opcodes to uses and defs in 835 * non-typed opcodes (such as MOVE). The Setxx(index) helpers are used to set defined 836 * types on typed opcodes (such as ADD_INT). The Setxx(index, is_xx) form is used to 837 * propagate types through non-typed opcodes such as PHI and MOVE. The is_xx flag 838 * tells whether our guess of the type is based on a previously typed definition. 839 * If so, the defined type takes precedence. Note that it's possible to have the same sreg 840 * show multiple defined types because dx treats constants as untyped bit patterns. 841 * The return value of the Setxx() helpers says whether or not the Setxx() action changed 842 * the current guess, and is used to know when to terminate the iterative walk. 843 */ 844 bool SetFp(int index, bool is_fp); 845 bool SetFp(int index); 846 bool SetCore(int index, bool is_core); 847 bool SetCore(int index); 848 bool SetRef(int index, bool is_ref); 849 bool SetRef(int index); 850 bool SetWide(int index, bool is_wide); 851 bool SetWide(int index); 852 bool SetHigh(int index, bool is_high); 853 bool SetHigh(int index); 854 855 char* GetDalvikDisassembly(const MIR* mir); 856 void ReplaceSpecialChars(std::string& str); 857 std::string GetSSAName(int ssa_reg); 858 std::string GetSSANameWithConst(int ssa_reg, bool singles_only); 859 void GetBlockName(BasicBlock* bb, char* name); 860 const char* GetShortyFromTargetIdx(int); 861 void DumpMIRGraph(); 862 CallInfo* NewMemCallInfo(BasicBlock* bb, MIR* mir, InvokeType type, bool is_range); 863 BasicBlock* NewMemBB(BBType block_type, int block_id); 864 MIR* NewMIR(); 865 MIR* AdvanceMIR(BasicBlock** p_bb, MIR* mir); 866 BasicBlock* NextDominatedBlock(BasicBlock* bb); 867 bool LayoutBlocks(BasicBlock* bb); 868 869 bool InlineCallsGate(); 870 void InlineCallsStart(); 871 void InlineCalls(BasicBlock* bb); 872 void InlineCallsEnd(); 873 874 /** 875 * @brief Perform the initial preparation for the Method Uses. 876 */ 877 void InitializeMethodUses(); 878 879 /** 880 * @brief Perform the initial preparation for the Constant Propagation. 881 */ 882 void InitializeConstantPropagation(); 883 884 /** 885 * @brief Perform the initial preparation for the SSA Transformation. 886 */ 887 void InitializeSSATransformation(); 888 889 /** 890 * @brief Insert a the operands for the Phi nodes. 891 * @param bb the considered BasicBlock. 892 * @return true 893 */ 894 bool InsertPhiNodeOperands(BasicBlock* bb); 895 896 /** 897 * @brief Perform constant propagation on a BasicBlock. 898 * @param bb the considered BasicBlock. 899 */ 900 void DoConstantPropagation(BasicBlock* bb); 901 902 /** 903 * @brief Count the uses in the BasicBlock 904 * @param bb the BasicBlock 905 */ 906 void CountUses(struct BasicBlock* bb); 907 908 static uint64_t GetDataFlowAttributes(Instruction::Code opcode); 909 static uint64_t GetDataFlowAttributes(MIR* mir); 910 911 /** 912 * @brief Combine BasicBlocks 913 * @param the BasicBlock we are considering 914 */ 915 void CombineBlocks(BasicBlock* bb); 916 917 void ClearAllVisitedFlags(); 918 /* 919 * IsDebugBuild sanity check: keep track of the Dex PCs for catch entries so that later on 920 * we can verify that all catch entries have native PC entries. 921 */ 922 std::set<uint32_t> catches_; 923 924 // TODO: make these private. 925 RegLocation* reg_location_; // Map SSA names to location. 926 SafeMap<unsigned int, unsigned int> block_id_map_; // Block collapse lookup cache. 927 928 static const char* extended_mir_op_names_[kMirOpLast - kMirOpFirst]; 929 static const uint32_t analysis_attributes_[kMirOpLast]; 930 931 void HandleSSADef(int* defs, int dalvik_reg, int reg_index); 932 bool InferTypeAndSize(BasicBlock* bb, MIR* mir, bool changed); 933 void ComputeDFSOrders(); 934 935 protected: 936 int FindCommonParent(int block1, int block2); 937 void ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1, 938 const ArenaBitVector* src2); 939 void HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v, 940 ArenaBitVector* live_in_v, int dalvik_reg_id); 941 void HandleDef(ArenaBitVector* def_v, int dalvik_reg_id); 942 void CompilerInitializeSSAConversion(); 943 bool DoSSAConversion(BasicBlock* bb); 944 bool InvokeUsesMethodStar(MIR* mir); 945 int ParseInsn(const uint16_t* code_ptr, MIR::DecodedInstruction* decoded_instruction); 946 bool ContentIsInsn(const uint16_t* code_ptr); 947 BasicBlock* SplitBlock(DexOffset code_offset, BasicBlock* orig_block, 948 BasicBlock** immed_pred_block_p); 949 BasicBlock* FindBlock(DexOffset code_offset, bool split, bool create, 950 BasicBlock** immed_pred_block_p); 951 void ProcessTryCatchBlocks(); 952 BasicBlock* ProcessCanBranch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 953 int flags, const uint16_t* code_ptr, const uint16_t* code_end); 954 BasicBlock* ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 955 int flags); 956 BasicBlock* ProcessCanThrow(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 957 int flags, ArenaBitVector* try_block_addr, const uint16_t* code_ptr, 958 const uint16_t* code_end); 959 int AddNewSReg(int v_reg); 960 void HandleSSAUse(int* uses, int dalvik_reg, int reg_index); 961 void DataFlowSSAFormat35C(MIR* mir); 962 void DataFlowSSAFormat3RC(MIR* mir); 963 bool FindLocalLiveIn(BasicBlock* bb); 964 bool VerifyPredInfo(BasicBlock* bb); 965 BasicBlock* NeedsVisit(BasicBlock* bb); 966 BasicBlock* NextUnvisitedSuccessor(BasicBlock* bb); 967 void MarkPreOrder(BasicBlock* bb); 968 void RecordDFSOrders(BasicBlock* bb); 969 void ComputeDefBlockMatrix(); 970 void ComputeDomPostOrderTraversal(BasicBlock* bb); 971 void ComputeDominators(); 972 void InsertPhiNodes(); 973 void DoDFSPreOrderSSARename(BasicBlock* block); 974 void SetConstant(int32_t ssa_reg, int value); 975 void SetConstantWide(int ssa_reg, int64_t value); 976 int GetSSAUseCount(int s_reg); 977 bool BasicBlockOpt(BasicBlock* bb); 978 bool BuildExtendedBBList(struct BasicBlock* bb); 979 bool FillDefBlockMatrix(BasicBlock* bb); 980 void InitializeDominationInfo(BasicBlock* bb); 981 bool ComputeblockIDom(BasicBlock* bb); 982 bool ComputeBlockDominators(BasicBlock* bb); 983 bool SetDominators(BasicBlock* bb); 984 bool ComputeBlockLiveIns(BasicBlock* bb); 985 bool ComputeDominanceFrontier(BasicBlock* bb); 986 987 void CountChecks(BasicBlock* bb); 988 void AnalyzeBlock(BasicBlock* bb, struct MethodStats* stats); 989 bool ComputeSkipCompilation(struct MethodStats* stats, bool skip_default); 990 991 CompilationUnit* const cu_; 992 GrowableArray<int>* ssa_base_vregs_; 993 GrowableArray<int>* ssa_subscripts_; 994 // Map original Dalvik virtual reg i to the current SSA name. 995 int* vreg_to_ssa_map_; // length == method->registers_size 996 int* ssa_last_defs_; // length == method->registers_size 997 ArenaBitVector* is_constant_v_; // length == num_ssa_reg 998 int* constant_values_; // length == num_ssa_reg 999 // Use counts of ssa names. 1000 GrowableArray<uint32_t> use_counts_; // Weighted by nesting depth 1001 GrowableArray<uint32_t> raw_use_counts_; // Not weighted 1002 unsigned int num_reachable_blocks_; 1003 GrowableArray<BasicBlockId>* dfs_order_; 1004 GrowableArray<BasicBlockId>* dfs_post_order_; 1005 GrowableArray<BasicBlockId>* dom_post_order_traversal_; 1006 int* i_dom_list_; 1007 ArenaBitVector** def_block_matrix_; // num_dalvik_register x num_blocks. 1008 ArenaBitVector* temp_dalvik_register_v_; 1009 std::unique_ptr<ScopedArenaAllocator> temp_scoped_alloc_; 1010 uint16_t* temp_insn_data_; 1011 uint32_t temp_bit_vector_size_; 1012 ArenaBitVector* temp_bit_vector_; 1013 static const int kInvalidEntry = -1; 1014 GrowableArray<BasicBlock*> block_list_; 1015 ArenaBitVector* try_block_addr_; 1016 BasicBlock* entry_block_; 1017 BasicBlock* exit_block_; 1018 int num_blocks_; 1019 const DexFile::CodeItem* current_code_item_; 1020 GrowableArray<uint16_t> dex_pc_to_block_map_; // FindBlock lookup cache. 1021 std::vector<DexCompilationUnit*> m_units_; // List of methods included in this graph 1022 typedef std::pair<int, int> MIRLocation; // Insert point, (m_unit_ index, offset) 1023 std::vector<MIRLocation> method_stack_; // Include stack 1024 int current_method_; 1025 DexOffset current_offset_; // Offset in code units 1026 int def_count_; // Used to estimate size of ssa name storage. 1027 int* opcode_count_; // Dex opcode coverage stats. 1028 int num_ssa_regs_; // Number of names following SSA transformation. 1029 std::vector<BasicBlockId> extended_basic_blocks_; // Heads of block "traces". 1030 int method_sreg_; 1031 unsigned int attributes_; 1032 Checkstats* checkstats_; 1033 ArenaAllocator* arena_; 1034 int backward_branches_; 1035 int forward_branches_; 1036 GrowableArray<CompilerTemp*> compiler_temps_; 1037 size_t num_non_special_compiler_temps_; 1038 size_t max_available_non_special_compiler_temps_; 1039 size_t max_available_special_compiler_temps_; 1040 bool punt_to_interpreter_; // Difficult or not worthwhile - just interpret. 1041 uint64_t merged_df_flags_; 1042 GrowableArray<MirIFieldLoweringInfo> ifield_lowering_infos_; 1043 GrowableArray<MirSFieldLoweringInfo> sfield_lowering_infos_; 1044 GrowableArray<MirMethodLoweringInfo> method_lowering_infos_; 1045 static const uint64_t oat_data_flow_attributes_[kMirOpLast]; 1046 1047 friend class ClassInitCheckEliminationTest; 1048 friend class LocalValueNumberingTest; 1049}; 1050 1051} // namespace art 1052 1053#endif // ART_COMPILER_DEX_MIR_GRAPH_H_ 1054