mir_graph.h revision 4896d7b6fb75add25f2d6ba84346ac83d8ba9d51
1/* 2 * Copyright (C) 2013 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_MIR_GRAPH_H_ 18#define ART_COMPILER_DEX_MIR_GRAPH_H_ 19 20#include <stdint.h> 21 22#include "dex_file.h" 23#include "dex_instruction.h" 24#include "compiler_ir.h" 25#include "invoke_type.h" 26#include "mir_field_info.h" 27#include "mir_method_info.h" 28#include "utils/arena_bit_vector.h" 29#include "utils/growable_array.h" 30#include "reg_storage.h" 31 32namespace art { 33 34enum InstructionAnalysisAttributePos { 35 kUninterestingOp = 0, 36 kArithmeticOp, 37 kFPOp, 38 kSingleOp, 39 kDoubleOp, 40 kIntOp, 41 kLongOp, 42 kBranchOp, 43 kInvokeOp, 44 kArrayOp, 45 kHeavyweightOp, 46 kSimpleConstOp, 47 kMoveOp, 48 kSwitch 49}; 50 51#define AN_NONE (1 << kUninterestingOp) 52#define AN_MATH (1 << kArithmeticOp) 53#define AN_FP (1 << kFPOp) 54#define AN_LONG (1 << kLongOp) 55#define AN_INT (1 << kIntOp) 56#define AN_SINGLE (1 << kSingleOp) 57#define AN_DOUBLE (1 << kDoubleOp) 58#define AN_FLOATMATH (1 << kFPOp) 59#define AN_BRANCH (1 << kBranchOp) 60#define AN_INVOKE (1 << kInvokeOp) 61#define AN_ARRAYOP (1 << kArrayOp) 62#define AN_HEAVYWEIGHT (1 << kHeavyweightOp) 63#define AN_SIMPLECONST (1 << kSimpleConstOp) 64#define AN_MOVE (1 << kMoveOp) 65#define AN_SWITCH (1 << kSwitch) 66#define AN_COMPUTATIONAL (AN_MATH | AN_ARRAYOP | AN_MOVE | AN_SIMPLECONST) 67 68enum DataFlowAttributePos { 69 kUA = 0, 70 kUB, 71 kUC, 72 kAWide, 73 kBWide, 74 kCWide, 75 kDA, 76 kIsMove, 77 kSetsConst, 78 kFormat35c, 79 kFormat3rc, 80 kNullCheckSrc0, // Null check of uses[0]. 81 kNullCheckSrc1, // Null check of uses[1]. 82 kNullCheckSrc2, // Null check of uses[2]. 83 kNullCheckOut0, // Null check out outgoing arg0. 84 kDstNonNull, // May assume dst is non-null. 85 kRetNonNull, // May assume retval is non-null. 86 kNullTransferSrc0, // Object copy src[0] -> dst. 87 kNullTransferSrcN, // Phi null check state transfer. 88 kRangeCheckSrc1, // Range check of uses[1]. 89 kRangeCheckSrc2, // Range check of uses[2]. 90 kRangeCheckSrc3, // Range check of uses[3]. 91 kFPA, 92 kFPB, 93 kFPC, 94 kCoreA, 95 kCoreB, 96 kCoreC, 97 kRefA, 98 kRefB, 99 kRefC, 100 kUsesMethodStar, // Implicit use of Method*. 101 kUsesIField, // Accesses an instance field (IGET/IPUT). 102 kUsesSField, // Accesses a static field (SGET/SPUT). 103 kDoLVN, // Worth computing local value numbers. 104}; 105 106#define DF_NOP UINT64_C(0) 107#define DF_UA (UINT64_C(1) << kUA) 108#define DF_UB (UINT64_C(1) << kUB) 109#define DF_UC (UINT64_C(1) << kUC) 110#define DF_A_WIDE (UINT64_C(1) << kAWide) 111#define DF_B_WIDE (UINT64_C(1) << kBWide) 112#define DF_C_WIDE (UINT64_C(1) << kCWide) 113#define DF_DA (UINT64_C(1) << kDA) 114#define DF_IS_MOVE (UINT64_C(1) << kIsMove) 115#define DF_SETS_CONST (UINT64_C(1) << kSetsConst) 116#define DF_FORMAT_35C (UINT64_C(1) << kFormat35c) 117#define DF_FORMAT_3RC (UINT64_C(1) << kFormat3rc) 118#define DF_NULL_CHK_0 (UINT64_C(1) << kNullCheckSrc0) 119#define DF_NULL_CHK_1 (UINT64_C(1) << kNullCheckSrc1) 120#define DF_NULL_CHK_2 (UINT64_C(1) << kNullCheckSrc2) 121#define DF_NULL_CHK_OUT0 (UINT64_C(1) << kNullCheckOut0) 122#define DF_NON_NULL_DST (UINT64_C(1) << kDstNonNull) 123#define DF_NON_NULL_RET (UINT64_C(1) << kRetNonNull) 124#define DF_NULL_TRANSFER_0 (UINT64_C(1) << kNullTransferSrc0) 125#define DF_NULL_TRANSFER_N (UINT64_C(1) << kNullTransferSrcN) 126#define DF_RANGE_CHK_1 (UINT64_C(1) << kRangeCheckSrc1) 127#define DF_RANGE_CHK_2 (UINT64_C(1) << kRangeCheckSrc2) 128#define DF_RANGE_CHK_3 (UINT64_C(1) << kRangeCheckSrc3) 129#define DF_FP_A (UINT64_C(1) << kFPA) 130#define DF_FP_B (UINT64_C(1) << kFPB) 131#define DF_FP_C (UINT64_C(1) << kFPC) 132#define DF_CORE_A (UINT64_C(1) << kCoreA) 133#define DF_CORE_B (UINT64_C(1) << kCoreB) 134#define DF_CORE_C (UINT64_C(1) << kCoreC) 135#define DF_REF_A (UINT64_C(1) << kRefA) 136#define DF_REF_B (UINT64_C(1) << kRefB) 137#define DF_REF_C (UINT64_C(1) << kRefC) 138#define DF_UMS (UINT64_C(1) << kUsesMethodStar) 139#define DF_IFIELD (UINT64_C(1) << kUsesIField) 140#define DF_SFIELD (UINT64_C(1) << kUsesSField) 141#define DF_LVN (UINT64_C(1) << kDoLVN) 142 143#define DF_HAS_USES (DF_UA | DF_UB | DF_UC) 144 145#define DF_HAS_DEFS (DF_DA) 146 147#define DF_HAS_NULL_CHKS (DF_NULL_CHK_0 | \ 148 DF_NULL_CHK_1 | \ 149 DF_NULL_CHK_2 | \ 150 DF_NULL_CHK_OUT0) 151 152#define DF_HAS_RANGE_CHKS (DF_RANGE_CHK_1 | \ 153 DF_RANGE_CHK_2 | \ 154 DF_RANGE_CHK_3) 155 156#define DF_HAS_NR_CHKS (DF_HAS_NULL_CHKS | \ 157 DF_HAS_RANGE_CHKS) 158 159#define DF_A_IS_REG (DF_UA | DF_DA) 160#define DF_B_IS_REG (DF_UB) 161#define DF_C_IS_REG (DF_UC) 162#define DF_IS_GETTER_OR_SETTER (DF_IS_GETTER | DF_IS_SETTER) 163#define DF_USES_FP (DF_FP_A | DF_FP_B | DF_FP_C) 164#define DF_NULL_TRANSFER (DF_NULL_TRANSFER_0 | DF_NULL_TRANSFER_N) 165enum OatMethodAttributes { 166 kIsLeaf, // Method is leaf. 167 kHasLoop, // Method contains simple loop. 168}; 169 170#define METHOD_IS_LEAF (1 << kIsLeaf) 171#define METHOD_HAS_LOOP (1 << kHasLoop) 172 173// Minimum field size to contain Dalvik v_reg number. 174#define VREG_NUM_WIDTH 16 175 176#define INVALID_SREG (-1) 177#define INVALID_VREG (0xFFFFU) 178#define INVALID_OFFSET (0xDEADF00FU) 179 180#define MIR_IGNORE_NULL_CHECK (1 << kMIRIgnoreNullCheck) 181#define MIR_NULL_CHECK_ONLY (1 << kMIRNullCheckOnly) 182#define MIR_IGNORE_RANGE_CHECK (1 << kMIRIgnoreRangeCheck) 183#define MIR_RANGE_CHECK_ONLY (1 << kMIRRangeCheckOnly) 184#define MIR_IGNORE_CLINIT_CHECK (1 << kMIRIgnoreClInitCheck) 185#define MIR_INLINED (1 << kMIRInlined) 186#define MIR_INLINED_PRED (1 << kMIRInlinedPred) 187#define MIR_CALLEE (1 << kMIRCallee) 188#define MIR_IGNORE_SUSPEND_CHECK (1 << kMIRIgnoreSuspendCheck) 189#define MIR_DUP (1 << kMIRDup) 190 191#define BLOCK_NAME_LEN 80 192 193typedef uint16_t BasicBlockId; 194static const BasicBlockId NullBasicBlockId = 0; 195 196/* 197 * In general, vreg/sreg describe Dalvik registers that originated with dx. However, 198 * it is useful to have compiler-generated temporary registers and have them treated 199 * in the same manner as dx-generated virtual registers. This struct records the SSA 200 * name of compiler-introduced temporaries. 201 */ 202struct CompilerTemp { 203 int32_t v_reg; // Virtual register number for temporary. 204 int32_t s_reg_low; // SSA name for low Dalvik word. 205}; 206 207enum CompilerTempType { 208 kCompilerTempVR, // A virtual register temporary. 209 kCompilerTempSpecialMethodPtr, // Temporary that keeps track of current method pointer. 210}; 211 212// When debug option enabled, records effectiveness of null and range check elimination. 213struct Checkstats { 214 int32_t null_checks; 215 int32_t null_checks_eliminated; 216 int32_t range_checks; 217 int32_t range_checks_eliminated; 218}; 219 220// Dataflow attributes of a basic block. 221struct BasicBlockDataFlow { 222 ArenaBitVector* use_v; 223 ArenaBitVector* def_v; 224 ArenaBitVector* live_in_v; 225 ArenaBitVector* phi_v; 226 int32_t* vreg_to_ssa_map_exit; 227 ArenaBitVector* ending_check_v; // For null check and class init check elimination. 228}; 229 230/* 231 * Normalized use/def for a MIR operation using SSA names rather than vregs. Note that 232 * uses/defs retain the Dalvik convention that long operations operate on a pair of 32-bit 233 * vregs. For example, "ADD_LONG v0, v2, v3" would have 2 defs (v0/v1) and 4 uses (v2/v3, v4/v5). 234 * Following SSA renaming, this is the primary struct used by code generators to locate 235 * operand and result registers. This is a somewhat confusing and unhelpful convention that 236 * we may want to revisit in the future. 237 * 238 * TODO: 239 * 1. Add accessors for uses/defs and make data private 240 * 2. Change fp_use/fp_def to a bit array (could help memory usage) 241 * 3. Combine array storage into internal array and handled via accessors from 1. 242 */ 243struct SSARepresentation { 244 int32_t* uses; 245 bool* fp_use; 246 int32_t* defs; 247 bool* fp_def; 248 int16_t num_uses_allocated; 249 int16_t num_defs_allocated; 250 int16_t num_uses; 251 int16_t num_defs; 252 253 static uint32_t GetStartUseIndex(Instruction::Code opcode); 254}; 255 256/* 257 * The Midlevel Intermediate Representation node, which may be largely considered a 258 * wrapper around a Dalvik byte code. 259 */ 260struct MIR { 261 /* 262 * TODO: remove embedded DecodedInstruction to save space, keeping only opcode. Recover 263 * additional fields on as-needed basis. Question: how to support MIR Pseudo-ops; probably 264 * need to carry aux data pointer. 265 */ 266 struct DecodedInstruction { 267 uint32_t vA; 268 uint32_t vB; 269 uint64_t vB_wide; /* for k51l */ 270 uint32_t vC; 271 uint32_t arg[5]; /* vC/D/E/F/G in invoke or filled-new-array */ 272 Instruction::Code opcode; 273 274 explicit DecodedInstruction():vA(0), vB(0), vB_wide(0), vC(0), opcode(Instruction::NOP) { 275 } 276 277 /* 278 * Given a decoded instruction representing a const bytecode, it updates 279 * the out arguments with proper values as dictated by the constant bytecode. 280 */ 281 bool GetConstant(int64_t* ptr_value, bool* wide) const; 282 283 bool IsStore() const { 284 return ((Instruction::FlagsOf(opcode) & Instruction::kStore) == Instruction::kStore); 285 } 286 287 bool IsLoad() const { 288 return ((Instruction::FlagsOf(opcode) & Instruction::kLoad) == Instruction::kLoad); 289 } 290 291 bool IsConditionalBranch() const { 292 return (Instruction::FlagsOf(opcode) == (Instruction::kContinue | Instruction::kBranch)); 293 } 294 295 /** 296 * @brief Is the register C component of the decoded instruction a constant? 297 */ 298 bool IsCFieldOrConstant() const { 299 return ((Instruction::FlagsOf(opcode) & Instruction::kRegCFieldOrConstant) == Instruction::kRegCFieldOrConstant); 300 } 301 302 /** 303 * @brief Is the register C component of the decoded instruction a constant? 304 */ 305 bool IsBFieldOrConstant() const { 306 return ((Instruction::FlagsOf(opcode) & Instruction::kRegBFieldOrConstant) == Instruction::kRegBFieldOrConstant); 307 } 308 309 bool IsCast() const { 310 return ((Instruction::FlagsOf(opcode) & Instruction::kCast) == Instruction::kCast); 311 } 312 313 /** 314 * @brief Does the instruction clobber memory? 315 * @details Clobber means that the instruction changes the memory not in a punctual way. 316 * Therefore any supposition on memory aliasing or memory contents should be disregarded 317 * when crossing such an instruction. 318 */ 319 bool Clobbers() const { 320 return ((Instruction::FlagsOf(opcode) & Instruction::kClobber) == Instruction::kClobber); 321 } 322 323 bool IsLinear() const { 324 return (Instruction::FlagsOf(opcode) & (Instruction::kAdd | Instruction::kSubtract)) != 0; 325 } 326 } dalvikInsn; 327 328 NarrowDexOffset offset; // Offset of the instruction in code units. 329 uint16_t optimization_flags; 330 int16_t m_unit_index; // From which method was this MIR included 331 BasicBlockId bb; 332 MIR* next; 333 SSARepresentation* ssa_rep; 334 union { 335 // Incoming edges for phi node. 336 BasicBlockId* phi_incoming; 337 // Establish link from check instruction (kMirOpCheck) to the actual throwing instruction. 338 MIR* throw_insn; 339 // Branch condition for fused cmp or select. 340 ConditionCode ccode; 341 // IGET/IPUT lowering info index, points to MIRGraph::ifield_lowering_infos_. Due to limit on 342 // the number of code points (64K) and size of IGET/IPUT insn (2), this will never exceed 32K. 343 uint32_t ifield_lowering_info; 344 // SGET/SPUT lowering info index, points to MIRGraph::sfield_lowering_infos_. Due to limit on 345 // the number of code points (64K) and size of SGET/SPUT insn (2), this will never exceed 32K. 346 uint32_t sfield_lowering_info; 347 // INVOKE data index, points to MIRGraph::method_lowering_infos_. 348 uint32_t method_lowering_info; 349 } meta; 350 351 explicit MIR():offset(0), optimization_flags(0), m_unit_index(0), bb(NullBasicBlockId), 352 next(nullptr), ssa_rep(nullptr) { 353 memset(&meta, 0, sizeof(meta)); 354 } 355 356 uint32_t GetStartUseIndex() const { 357 return SSARepresentation::GetStartUseIndex(dalvikInsn.opcode); 358 } 359 360 MIR* Copy(CompilationUnit *c_unit); 361 MIR* Copy(MIRGraph* mir_Graph); 362 363 static void* operator new(size_t size, ArenaAllocator* arena) { 364 return arena->Alloc(sizeof(MIR), kArenaAllocMIR); 365 } 366 static void operator delete(void* p) {} // Nop. 367}; 368 369struct SuccessorBlockInfo; 370 371struct BasicBlock { 372 BasicBlockId id; 373 BasicBlockId dfs_id; 374 NarrowDexOffset start_offset; // Offset in code units. 375 BasicBlockId fall_through; 376 BasicBlockId taken; 377 BasicBlockId i_dom; // Immediate dominator. 378 uint16_t nesting_depth; 379 BBType block_type:4; 380 BlockListType successor_block_list_type:4; 381 bool visited:1; 382 bool hidden:1; 383 bool catch_entry:1; 384 bool explicit_throw:1; 385 bool conditional_branch:1; 386 bool terminated_by_return:1; // Block ends with a Dalvik return opcode. 387 bool dominates_return:1; // Is a member of return extended basic block. 388 bool use_lvn:1; // Run local value numbering on this block. 389 MIR* first_mir_insn; 390 MIR* last_mir_insn; 391 BasicBlockDataFlow* data_flow_info; 392 ArenaBitVector* dominators; 393 ArenaBitVector* i_dominated; // Set nodes being immediately dominated. 394 ArenaBitVector* dom_frontier; // Dominance frontier. 395 GrowableArray<BasicBlockId>* predecessors; 396 GrowableArray<SuccessorBlockInfo*>* successor_blocks; 397 398 void AppendMIR(MIR* mir); 399 void AppendMIRList(MIR* first_list_mir, MIR* last_list_mir); 400 void AppendMIRList(const std::vector<MIR*>& insns); 401 void PrependMIR(MIR* mir); 402 void PrependMIRList(MIR* first_list_mir, MIR* last_list_mir); 403 void PrependMIRList(const std::vector<MIR*>& to_add); 404 void InsertMIRAfter(MIR* current_mir, MIR* new_mir); 405 void InsertMIRListAfter(MIR* insert_after, MIR* first_list_mir, MIR* last_list_mir); 406 MIR* FindPreviousMIR(MIR* mir); 407 void InsertMIRBefore(MIR* insert_before, MIR* list); 408 void InsertMIRListBefore(MIR* insert_before, MIR* first_list_mir, MIR* last_list_mir); 409 bool RemoveMIR(MIR* mir); 410 bool RemoveMIRList(MIR* first_list_mir, MIR* last_list_mir); 411 412 BasicBlock* Copy(CompilationUnit* c_unit); 413 BasicBlock* Copy(MIRGraph* mir_graph); 414 415 /** 416 * @brief Reset the optimization_flags field of each MIR. 417 */ 418 void ResetOptimizationFlags(uint16_t reset_flags); 419 420 /** 421 * @brief Hide the BasicBlock. 422 * @details Set it to kDalvikByteCode, set hidden to true, remove all MIRs, 423 * remove itself from any predecessor edges, remove itself from any 424 * child's predecessor growable array. 425 */ 426 void Hide(CompilationUnit* c_unit); 427 428 /** 429 * @brief Is ssa_reg the last SSA definition of that VR in the block? 430 */ 431 bool IsSSALiveOut(const CompilationUnit* c_unit, int ssa_reg); 432 433 /** 434 * @brief Replace the edge going to old_bb to now go towards new_bb. 435 */ 436 bool ReplaceChild(BasicBlockId old_bb, BasicBlockId new_bb); 437 438 /** 439 * @brief Update the predecessor growable array from old_pred to new_pred. 440 */ 441 void UpdatePredecessor(BasicBlockId old_pred, BasicBlockId new_pred); 442 443 /** 444 * @brief Used to obtain the next MIR that follows unconditionally. 445 * @details The implementation does not guarantee that a MIR does not 446 * follow even if this method returns nullptr. 447 * @param mir_graph the MIRGraph. 448 * @param current The MIR for which to find an unconditional follower. 449 * @return Returns the following MIR if one can be found. 450 */ 451 MIR* GetNextUnconditionalMir(MIRGraph* mir_graph, MIR* current); 452 bool IsExceptionBlock() const; 453 454 static void* operator new(size_t size, ArenaAllocator* arena) { 455 return arena->Alloc(sizeof(BasicBlock), kArenaAllocBB); 456 } 457 static void operator delete(void* p) {} // Nop. 458}; 459 460/* 461 * The "blocks" field in "successor_block_list" points to an array of elements with the type 462 * "SuccessorBlockInfo". For catch blocks, key is type index for the exception. For switch 463 * blocks, key is the case value. 464 */ 465struct SuccessorBlockInfo { 466 BasicBlockId block; 467 int key; 468}; 469 470/** 471 * @class ChildBlockIterator 472 * @brief Enable an easy iteration of the children. 473 */ 474class ChildBlockIterator { 475 public: 476 /** 477 * @brief Constructs a child iterator. 478 * @param bb The basic whose children we need to iterate through. 479 * @param mir_graph The MIRGraph used to get the basic block during iteration. 480 */ 481 ChildBlockIterator(BasicBlock* bb, MIRGraph* mir_graph); 482 BasicBlock* Next(); 483 484 private: 485 BasicBlock* basic_block_; 486 MIRGraph* mir_graph_; 487 bool visited_fallthrough_; 488 bool visited_taken_; 489 bool have_successors_; 490 GrowableArray<SuccessorBlockInfo*>::Iterator successor_iter_; 491}; 492 493/* 494 * Whereas a SSA name describes a definition of a Dalvik vreg, the RegLocation describes 495 * the type of an SSA name (and, can also be used by code generators to record where the 496 * value is located (i.e. - physical register, frame, spill, etc.). For each SSA name (SReg) 497 * there is a RegLocation. 498 * A note on SSA names: 499 * o SSA names for Dalvik vRegs v0..vN will be assigned 0..N. These represent the "vN_0" 500 * names. Negative SSA names represent special values not present in the Dalvik byte code. 501 * For example, SSA name -1 represents an invalid SSA name, and SSA name -2 represents the 502 * the Method pointer. SSA names < -2 are reserved for future use. 503 * o The vN_0 names for non-argument Dalvik should in practice never be used (as they would 504 * represent the read of an undefined local variable). The first definition of the 505 * underlying Dalvik vReg will result in a vN_1 name. 506 * 507 * FIXME: The orig_sreg field was added as a workaround for llvm bitcode generation. With 508 * the latest restructuring, we should be able to remove it and rely on s_reg_low throughout. 509 */ 510struct RegLocation { 511 RegLocationType location:3; 512 unsigned wide:1; 513 unsigned defined:1; // Do we know the type? 514 unsigned is_const:1; // Constant, value in mir_graph->constant_values[]. 515 unsigned fp:1; // Floating point? 516 unsigned core:1; // Non-floating point? 517 unsigned ref:1; // Something GC cares about. 518 unsigned high_word:1; // High word of pair? 519 unsigned home:1; // Does this represent the home location? 520 RegStorage reg; // Encoded physical registers. 521 int16_t s_reg_low; // SSA name for low Dalvik word. 522 int16_t orig_sreg; // TODO: remove after Bitcode gen complete 523 // and consolidate usage w/ s_reg_low. 524}; 525 526/* 527 * Collection of information describing an invoke, and the destination of 528 * the subsequent MOVE_RESULT (if applicable). Collected as a unit to enable 529 * more efficient invoke code generation. 530 */ 531struct CallInfo { 532 int num_arg_words; // Note: word count, not arg count. 533 RegLocation* args; // One for each word of arguments. 534 RegLocation result; // Eventual target of MOVE_RESULT. 535 int opt_flags; 536 InvokeType type; 537 uint32_t dex_idx; 538 uint32_t index; // Method idx for invokes, type idx for FilledNewArray. 539 uintptr_t direct_code; 540 uintptr_t direct_method; 541 RegLocation target; // Target of following move_result. 542 bool skip_this; 543 bool is_range; 544 DexOffset offset; // Offset in code units. 545 MIR* mir; 546}; 547 548 549const RegLocation bad_loc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0, 0, RegStorage(), INVALID_SREG, 550 INVALID_SREG}; 551 552class MIRGraph { 553 public: 554 MIRGraph(CompilationUnit* cu, ArenaAllocator* arena); 555 ~MIRGraph(); 556 557 /* 558 * Examine the graph to determine whether it's worthwile to spend the time compiling 559 * this method. 560 */ 561 bool SkipCompilation(); 562 563 /* 564 * Should we skip the compilation of this method based on its name? 565 */ 566 bool SkipCompilation(const std::string& methodname); 567 568 /* 569 * Parse dex method and add MIR at current insert point. Returns id (which is 570 * actually the index of the method in the m_units_ array). 571 */ 572 void InlineMethod(const DexFile::CodeItem* code_item, uint32_t access_flags, 573 InvokeType invoke_type, uint16_t class_def_idx, 574 uint32_t method_idx, jobject class_loader, const DexFile& dex_file); 575 576 /* Find existing block */ 577 BasicBlock* FindBlock(DexOffset code_offset) { 578 return FindBlock(code_offset, false, false, NULL); 579 } 580 581 const uint16_t* GetCurrentInsns() const { 582 return current_code_item_->insns_; 583 } 584 585 const uint16_t* GetInsns(int m_unit_index) const { 586 return m_units_[m_unit_index]->GetCodeItem()->insns_; 587 } 588 589 int GetNumBlocks() const { 590 return num_blocks_; 591 } 592 593 size_t GetNumDalvikInsns() const { 594 return cu_->code_item->insns_size_in_code_units_; 595 } 596 597 ArenaBitVector* GetTryBlockAddr() const { 598 return try_block_addr_; 599 } 600 601 BasicBlock* GetEntryBlock() const { 602 return entry_block_; 603 } 604 605 BasicBlock* GetExitBlock() const { 606 return exit_block_; 607 } 608 609 BasicBlock* GetBasicBlock(int block_id) const { 610 return (block_id == NullBasicBlockId) ? NULL : block_list_.Get(block_id); 611 } 612 613 size_t GetBasicBlockListCount() const { 614 return block_list_.Size(); 615 } 616 617 GrowableArray<BasicBlock*>* GetBlockList() { 618 return &block_list_; 619 } 620 621 GrowableArray<BasicBlockId>* GetDfsOrder() { 622 return dfs_order_; 623 } 624 625 GrowableArray<BasicBlockId>* GetDfsPostOrder() { 626 return dfs_post_order_; 627 } 628 629 GrowableArray<BasicBlockId>* GetDomPostOrder() { 630 return dom_post_order_traversal_; 631 } 632 633 int GetDefCount() const { 634 return def_count_; 635 } 636 637 ArenaAllocator* GetArena() { 638 return arena_; 639 } 640 641 void EnableOpcodeCounting() { 642 opcode_count_ = static_cast<int*>(arena_->Alloc(kNumPackedOpcodes * sizeof(int), 643 kArenaAllocMisc)); 644 } 645 646 void ShowOpcodeStats(); 647 648 DexCompilationUnit* GetCurrentDexCompilationUnit() const { 649 return m_units_[current_method_]; 650 } 651 652 /** 653 * @brief Dump a CFG into a dot file format. 654 * @param dir_prefix the directory the file will be created in. 655 * @param all_blocks does the dumper use all the basic blocks or use the reachable blocks. 656 * @param suffix does the filename require a suffix or not (default = nullptr). 657 */ 658 void DumpCFG(const char* dir_prefix, bool all_blocks, const char* suffix = nullptr); 659 660 bool HasFieldAccess() const { 661 return (merged_df_flags_ & (DF_IFIELD | DF_SFIELD)) != 0u; 662 } 663 664 bool HasStaticFieldAccess() const { 665 return (merged_df_flags_ & DF_SFIELD) != 0u; 666 } 667 668 bool HasInvokes() const { 669 // NOTE: These formats include the rare filled-new-array/range. 670 return (merged_df_flags_ & (DF_FORMAT_35C | DF_FORMAT_3RC)) != 0u; 671 } 672 673 void DoCacheFieldLoweringInfo(); 674 675 const MirIFieldLoweringInfo& GetIFieldLoweringInfo(MIR* mir) const { 676 DCHECK_LT(mir->meta.ifield_lowering_info, ifield_lowering_infos_.Size()); 677 return ifield_lowering_infos_.GetRawStorage()[mir->meta.ifield_lowering_info]; 678 } 679 680 const MirSFieldLoweringInfo& GetSFieldLoweringInfo(MIR* mir) const { 681 DCHECK_LT(mir->meta.sfield_lowering_info, sfield_lowering_infos_.Size()); 682 return sfield_lowering_infos_.GetRawStorage()[mir->meta.sfield_lowering_info]; 683 } 684 685 void DoCacheMethodLoweringInfo(); 686 687 const MirMethodLoweringInfo& GetMethodLoweringInfo(MIR* mir) { 688 DCHECK_LT(mir->meta.method_lowering_info, method_lowering_infos_.Size()); 689 return method_lowering_infos_.GetRawStorage()[mir->meta.method_lowering_info]; 690 } 691 692 void ComputeInlineIFieldLoweringInfo(uint16_t field_idx, MIR* invoke, MIR* iget_or_iput); 693 694 void InitRegLocations(); 695 696 void RemapRegLocations(); 697 698 void DumpRegLocTable(RegLocation* table, int count); 699 700 void BasicBlockOptimization(); 701 702 GrowableArray<BasicBlockId>* GetTopologicalSortOrder() { 703 return topological_order_; 704 } 705 706 bool IsConst(int32_t s_reg) const { 707 return is_constant_v_->IsBitSet(s_reg); 708 } 709 710 bool IsConst(RegLocation loc) const { 711 return loc.orig_sreg < 0 ? false : IsConst(loc.orig_sreg); 712 } 713 714 int32_t ConstantValue(RegLocation loc) const { 715 DCHECK(IsConst(loc)); 716 return constant_values_[loc.orig_sreg]; 717 } 718 719 int32_t ConstantValue(int32_t s_reg) const { 720 DCHECK(IsConst(s_reg)); 721 return constant_values_[s_reg]; 722 } 723 724 int64_t ConstantValueWide(RegLocation loc) const { 725 DCHECK(IsConst(loc)); 726 return (static_cast<int64_t>(constant_values_[loc.orig_sreg + 1]) << 32) | 727 Low32Bits(static_cast<int64_t>(constant_values_[loc.orig_sreg])); 728 } 729 730 bool IsConstantNullRef(RegLocation loc) const { 731 return loc.ref && loc.is_const && (ConstantValue(loc) == 0); 732 } 733 734 int GetNumSSARegs() const { 735 return num_ssa_regs_; 736 } 737 738 void SetNumSSARegs(int new_num) { 739 /* 740 * TODO: It's theoretically possible to exceed 32767, though any cases which did 741 * would be filtered out with current settings. When orig_sreg field is removed 742 * from RegLocation, expand s_reg_low to handle all possible cases and remove DCHECK(). 743 */ 744 DCHECK_EQ(new_num, static_cast<int16_t>(new_num)); 745 num_ssa_regs_ = new_num; 746 } 747 748 unsigned int GetNumReachableBlocks() const { 749 return num_reachable_blocks_; 750 } 751 752 int GetUseCount(int vreg) const { 753 return use_counts_.Get(vreg); 754 } 755 756 int GetRawUseCount(int vreg) const { 757 return raw_use_counts_.Get(vreg); 758 } 759 760 int GetSSASubscript(int ssa_reg) const { 761 return ssa_subscripts_->Get(ssa_reg); 762 } 763 764 RegLocation GetRawSrc(MIR* mir, int num) { 765 DCHECK(num < mir->ssa_rep->num_uses); 766 RegLocation res = reg_location_[mir->ssa_rep->uses[num]]; 767 return res; 768 } 769 770 RegLocation GetRawDest(MIR* mir) { 771 DCHECK_GT(mir->ssa_rep->num_defs, 0); 772 RegLocation res = reg_location_[mir->ssa_rep->defs[0]]; 773 return res; 774 } 775 776 RegLocation GetDest(MIR* mir) { 777 RegLocation res = GetRawDest(mir); 778 DCHECK(!res.wide); 779 return res; 780 } 781 782 RegLocation GetSrc(MIR* mir, int num) { 783 RegLocation res = GetRawSrc(mir, num); 784 DCHECK(!res.wide); 785 return res; 786 } 787 788 RegLocation GetDestWide(MIR* mir) { 789 RegLocation res = GetRawDest(mir); 790 DCHECK(res.wide); 791 return res; 792 } 793 794 RegLocation GetSrcWide(MIR* mir, int low) { 795 RegLocation res = GetRawSrc(mir, low); 796 DCHECK(res.wide); 797 return res; 798 } 799 800 RegLocation GetBadLoc() { 801 return bad_loc; 802 } 803 804 int GetMethodSReg() const { 805 return method_sreg_; 806 } 807 808 /** 809 * @brief Used to obtain the number of compiler temporaries being used. 810 * @return Returns the number of compiler temporaries. 811 */ 812 size_t GetNumUsedCompilerTemps() const { 813 size_t total_num_temps = compiler_temps_.Size(); 814 DCHECK_LE(num_non_special_compiler_temps_, total_num_temps); 815 return total_num_temps; 816 } 817 818 /** 819 * @brief Used to obtain the number of non-special compiler temporaries being used. 820 * @return Returns the number of non-special compiler temporaries. 821 */ 822 size_t GetNumNonSpecialCompilerTemps() const { 823 return num_non_special_compiler_temps_; 824 } 825 826 /** 827 * @brief Used to set the total number of available non-special compiler temporaries. 828 * @details Can fail setting the new max if there are more temps being used than the new_max. 829 * @param new_max The new maximum number of non-special compiler temporaries. 830 * @return Returns true if the max was set and false if failed to set. 831 */ 832 bool SetMaxAvailableNonSpecialCompilerTemps(size_t new_max) { 833 if (new_max < GetNumNonSpecialCompilerTemps()) { 834 return false; 835 } else { 836 max_available_non_special_compiler_temps_ = new_max; 837 return true; 838 } 839 } 840 841 /** 842 * @brief Provides the number of non-special compiler temps available. 843 * @details Even if this returns zero, special compiler temps are guaranteed to be available. 844 * @return Returns the number of available temps. 845 */ 846 size_t GetNumAvailableNonSpecialCompilerTemps(); 847 848 /** 849 * @brief Used to obtain an existing compiler temporary. 850 * @param index The index of the temporary which must be strictly less than the 851 * number of temporaries. 852 * @return Returns the temporary that was asked for. 853 */ 854 CompilerTemp* GetCompilerTemp(size_t index) const { 855 return compiler_temps_.Get(index); 856 } 857 858 /** 859 * @brief Used to obtain the maximum number of compiler temporaries that can be requested. 860 * @return Returns the maximum number of compiler temporaries, whether used or not. 861 */ 862 size_t GetMaxPossibleCompilerTemps() const { 863 return max_available_special_compiler_temps_ + max_available_non_special_compiler_temps_; 864 } 865 866 /** 867 * @brief Used to obtain a new unique compiler temporary. 868 * @param ct_type Type of compiler temporary requested. 869 * @param wide Whether we should allocate a wide temporary. 870 * @return Returns the newly created compiler temporary. 871 */ 872 CompilerTemp* GetNewCompilerTemp(CompilerTempType ct_type, bool wide); 873 874 bool MethodIsLeaf() { 875 return attributes_ & METHOD_IS_LEAF; 876 } 877 878 RegLocation GetRegLocation(int index) { 879 DCHECK((index >= 0) && (index < num_ssa_regs_)); 880 return reg_location_[index]; 881 } 882 883 RegLocation GetMethodLoc() { 884 return reg_location_[method_sreg_]; 885 } 886 887 bool IsBackedge(BasicBlock* branch_bb, BasicBlockId target_bb_id) { 888 return ((target_bb_id != NullBasicBlockId) && 889 (GetBasicBlock(target_bb_id)->start_offset <= branch_bb->start_offset)); 890 } 891 892 bool IsBackwardsBranch(BasicBlock* branch_bb) { 893 return IsBackedge(branch_bb, branch_bb->taken) || IsBackedge(branch_bb, branch_bb->fall_through); 894 } 895 896 void CountBranch(DexOffset target_offset) { 897 if (target_offset <= current_offset_) { 898 backward_branches_++; 899 } else { 900 forward_branches_++; 901 } 902 } 903 904 int GetBranchCount() { 905 return backward_branches_ + forward_branches_; 906 } 907 908 bool IsPseudoMirOp(Instruction::Code opcode) { 909 return static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst); 910 } 911 912 bool IsPseudoMirOp(int opcode) { 913 return opcode >= static_cast<int>(kMirOpFirst); 914 } 915 916 // Is this vreg in the in set? 917 bool IsInVReg(int vreg) { 918 return (vreg >= cu_->num_regs); 919 } 920 921 void DumpCheckStats(); 922 MIR* FindMoveResult(BasicBlock* bb, MIR* mir); 923 int SRegToVReg(int ssa_reg) const; 924 void VerifyDataflow(); 925 void CheckForDominanceFrontier(BasicBlock* dom_bb, const BasicBlock* succ_bb); 926 void EliminateNullChecksAndInferTypesStart(); 927 bool EliminateNullChecksAndInferTypes(BasicBlock *bb); 928 void EliminateNullChecksAndInferTypesEnd(); 929 bool EliminateClassInitChecksGate(); 930 bool EliminateClassInitChecks(BasicBlock* bb); 931 void EliminateClassInitChecksEnd(); 932 /* 933 * Type inference handling helpers. Because Dalvik's bytecode is not fully typed, 934 * we have to do some work to figure out the sreg type. For some operations it is 935 * clear based on the opcode (i.e. ADD_FLOAT v0, v1, v2), but for others (MOVE), we 936 * may never know the "real" type. 937 * 938 * We perform the type inference operation by using an iterative walk over 939 * the graph, propagating types "defined" by typed opcodes to uses and defs in 940 * non-typed opcodes (such as MOVE). The Setxx(index) helpers are used to set defined 941 * types on typed opcodes (such as ADD_INT). The Setxx(index, is_xx) form is used to 942 * propagate types through non-typed opcodes such as PHI and MOVE. The is_xx flag 943 * tells whether our guess of the type is based on a previously typed definition. 944 * If so, the defined type takes precedence. Note that it's possible to have the same sreg 945 * show multiple defined types because dx treats constants as untyped bit patterns. 946 * The return value of the Setxx() helpers says whether or not the Setxx() action changed 947 * the current guess, and is used to know when to terminate the iterative walk. 948 */ 949 bool SetFp(int index, bool is_fp); 950 bool SetFp(int index); 951 bool SetCore(int index, bool is_core); 952 bool SetCore(int index); 953 bool SetRef(int index, bool is_ref); 954 bool SetRef(int index); 955 bool SetWide(int index, bool is_wide); 956 bool SetWide(int index); 957 bool SetHigh(int index, bool is_high); 958 bool SetHigh(int index); 959 960 char* GetDalvikDisassembly(const MIR* mir); 961 void ReplaceSpecialChars(std::string& str); 962 std::string GetSSAName(int ssa_reg); 963 std::string GetSSANameWithConst(int ssa_reg, bool singles_only); 964 void GetBlockName(BasicBlock* bb, char* name); 965 const char* GetShortyFromTargetIdx(int); 966 void DumpMIRGraph(); 967 CallInfo* NewMemCallInfo(BasicBlock* bb, MIR* mir, InvokeType type, bool is_range); 968 BasicBlock* NewMemBB(BBType block_type, int block_id); 969 MIR* NewMIR(); 970 MIR* AdvanceMIR(BasicBlock** p_bb, MIR* mir); 971 BasicBlock* NextDominatedBlock(BasicBlock* bb); 972 bool LayoutBlocks(BasicBlock* bb); 973 void ComputeTopologicalSortOrder(); 974 BasicBlock* CreateNewBB(BBType block_type); 975 976 bool InlineCallsGate(); 977 void InlineCallsStart(); 978 void InlineCalls(BasicBlock* bb); 979 void InlineCallsEnd(); 980 981 /** 982 * @brief Perform the initial preparation for the Method Uses. 983 */ 984 void InitializeMethodUses(); 985 986 /** 987 * @brief Perform the initial preparation for the Constant Propagation. 988 */ 989 void InitializeConstantPropagation(); 990 991 /** 992 * @brief Perform the initial preparation for the SSA Transformation. 993 */ 994 void SSATransformationStart(); 995 996 /** 997 * @brief Insert a the operands for the Phi nodes. 998 * @param bb the considered BasicBlock. 999 * @return true 1000 */ 1001 bool InsertPhiNodeOperands(BasicBlock* bb); 1002 1003 /** 1004 * @brief Perform the cleanup after the SSA Transformation. 1005 */ 1006 void SSATransformationEnd(); 1007 1008 /** 1009 * @brief Perform constant propagation on a BasicBlock. 1010 * @param bb the considered BasicBlock. 1011 */ 1012 void DoConstantPropagation(BasicBlock* bb); 1013 1014 /** 1015 * @brief Count the uses in the BasicBlock 1016 * @param bb the BasicBlock 1017 */ 1018 void CountUses(struct BasicBlock* bb); 1019 1020 static uint64_t GetDataFlowAttributes(Instruction::Code opcode); 1021 static uint64_t GetDataFlowAttributes(MIR* mir); 1022 1023 /** 1024 * @brief Combine BasicBlocks 1025 * @param the BasicBlock we are considering 1026 */ 1027 void CombineBlocks(BasicBlock* bb); 1028 1029 void ClearAllVisitedFlags(); 1030 1031 void AllocateSSAUseData(MIR *mir, int num_uses); 1032 void AllocateSSADefData(MIR *mir, int num_defs); 1033 1034 /* 1035 * IsDebugBuild sanity check: keep track of the Dex PCs for catch entries so that later on 1036 * we can verify that all catch entries have native PC entries. 1037 */ 1038 std::set<uint32_t> catches_; 1039 1040 // TODO: make these private. 1041 RegLocation* reg_location_; // Map SSA names to location. 1042 SafeMap<unsigned int, unsigned int> block_id_map_; // Block collapse lookup cache. 1043 1044 static const char* extended_mir_op_names_[kMirOpLast - kMirOpFirst]; 1045 static const uint32_t analysis_attributes_[kMirOpLast]; 1046 1047 void HandleSSADef(int* defs, int dalvik_reg, int reg_index); 1048 bool InferTypeAndSize(BasicBlock* bb, MIR* mir, bool changed); 1049 void ComputeDFSOrders(); 1050 1051 protected: 1052 int FindCommonParent(int block1, int block2); 1053 void ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1, 1054 const ArenaBitVector* src2); 1055 void HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v, 1056 ArenaBitVector* live_in_v, int dalvik_reg_id); 1057 void HandleDef(ArenaBitVector* def_v, int dalvik_reg_id); 1058 void CompilerInitializeSSAConversion(); 1059 bool DoSSAConversion(BasicBlock* bb); 1060 bool InvokeUsesMethodStar(MIR* mir); 1061 int ParseInsn(const uint16_t* code_ptr, MIR::DecodedInstruction* decoded_instruction); 1062 bool ContentIsInsn(const uint16_t* code_ptr); 1063 BasicBlock* SplitBlock(DexOffset code_offset, BasicBlock* orig_block, 1064 BasicBlock** immed_pred_block_p); 1065 BasicBlock* FindBlock(DexOffset code_offset, bool split, bool create, 1066 BasicBlock** immed_pred_block_p); 1067 void ProcessTryCatchBlocks(); 1068 BasicBlock* ProcessCanBranch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 1069 int flags, const uint16_t* code_ptr, const uint16_t* code_end); 1070 BasicBlock* ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 1071 int flags); 1072 BasicBlock* ProcessCanThrow(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 1073 int flags, ArenaBitVector* try_block_addr, const uint16_t* code_ptr, 1074 const uint16_t* code_end); 1075 int AddNewSReg(int v_reg); 1076 void HandleSSAUse(int* uses, int dalvik_reg, int reg_index); 1077 void DataFlowSSAFormat35C(MIR* mir); 1078 void DataFlowSSAFormat3RC(MIR* mir); 1079 bool FindLocalLiveIn(BasicBlock* bb); 1080 bool VerifyPredInfo(BasicBlock* bb); 1081 BasicBlock* NeedsVisit(BasicBlock* bb); 1082 BasicBlock* NextUnvisitedSuccessor(BasicBlock* bb); 1083 void MarkPreOrder(BasicBlock* bb); 1084 void RecordDFSOrders(BasicBlock* bb); 1085 void ComputeDefBlockMatrix(); 1086 void ComputeDomPostOrderTraversal(BasicBlock* bb); 1087 void ComputeDominators(); 1088 void InsertPhiNodes(); 1089 void DoDFSPreOrderSSARename(BasicBlock* block); 1090 void SetConstant(int32_t ssa_reg, int value); 1091 void SetConstantWide(int ssa_reg, int64_t value); 1092 int GetSSAUseCount(int s_reg); 1093 bool BasicBlockOpt(BasicBlock* bb); 1094 bool BuildExtendedBBList(struct BasicBlock* bb); 1095 bool FillDefBlockMatrix(BasicBlock* bb); 1096 void InitializeDominationInfo(BasicBlock* bb); 1097 bool ComputeblockIDom(BasicBlock* bb); 1098 bool ComputeBlockDominators(BasicBlock* bb); 1099 bool SetDominators(BasicBlock* bb); 1100 bool ComputeBlockLiveIns(BasicBlock* bb); 1101 bool ComputeDominanceFrontier(BasicBlock* bb); 1102 1103 void CountChecks(BasicBlock* bb); 1104 void AnalyzeBlock(BasicBlock* bb, struct MethodStats* stats); 1105 bool ComputeSkipCompilation(struct MethodStats* stats, bool skip_default); 1106 1107 CompilationUnit* const cu_; 1108 GrowableArray<int>* ssa_base_vregs_; 1109 GrowableArray<int>* ssa_subscripts_; 1110 // Map original Dalvik virtual reg i to the current SSA name. 1111 int* vreg_to_ssa_map_; // length == method->registers_size 1112 int* ssa_last_defs_; // length == method->registers_size 1113 ArenaBitVector* is_constant_v_; // length == num_ssa_reg 1114 int* constant_values_; // length == num_ssa_reg 1115 // Use counts of ssa names. 1116 GrowableArray<uint32_t> use_counts_; // Weighted by nesting depth 1117 GrowableArray<uint32_t> raw_use_counts_; // Not weighted 1118 unsigned int num_reachable_blocks_; 1119 unsigned int max_num_reachable_blocks_; 1120 GrowableArray<BasicBlockId>* dfs_order_; 1121 GrowableArray<BasicBlockId>* dfs_post_order_; 1122 GrowableArray<BasicBlockId>* dom_post_order_traversal_; 1123 GrowableArray<BasicBlockId>* topological_order_; 1124 int* i_dom_list_; 1125 ArenaBitVector** def_block_matrix_; // num_dalvik_register x num_blocks. 1126 std::unique_ptr<ScopedArenaAllocator> temp_scoped_alloc_; 1127 uint16_t* temp_insn_data_; 1128 uint32_t temp_bit_vector_size_; 1129 ArenaBitVector* temp_bit_vector_; 1130 static const int kInvalidEntry = -1; 1131 GrowableArray<BasicBlock*> block_list_; 1132 ArenaBitVector* try_block_addr_; 1133 BasicBlock* entry_block_; 1134 BasicBlock* exit_block_; 1135 int num_blocks_; 1136 const DexFile::CodeItem* current_code_item_; 1137 GrowableArray<uint16_t> dex_pc_to_block_map_; // FindBlock lookup cache. 1138 std::vector<DexCompilationUnit*> m_units_; // List of methods included in this graph 1139 typedef std::pair<int, int> MIRLocation; // Insert point, (m_unit_ index, offset) 1140 std::vector<MIRLocation> method_stack_; // Include stack 1141 int current_method_; 1142 DexOffset current_offset_; // Offset in code units 1143 int def_count_; // Used to estimate size of ssa name storage. 1144 int* opcode_count_; // Dex opcode coverage stats. 1145 int num_ssa_regs_; // Number of names following SSA transformation. 1146 std::vector<BasicBlockId> extended_basic_blocks_; // Heads of block "traces". 1147 int method_sreg_; 1148 unsigned int attributes_; 1149 Checkstats* checkstats_; 1150 ArenaAllocator* arena_; 1151 int backward_branches_; 1152 int forward_branches_; 1153 GrowableArray<CompilerTemp*> compiler_temps_; 1154 size_t num_non_special_compiler_temps_; 1155 size_t max_available_non_special_compiler_temps_; 1156 size_t max_available_special_compiler_temps_; 1157 bool punt_to_interpreter_; // Difficult or not worthwhile - just interpret. 1158 uint64_t merged_df_flags_; 1159 GrowableArray<MirIFieldLoweringInfo> ifield_lowering_infos_; 1160 GrowableArray<MirSFieldLoweringInfo> sfield_lowering_infos_; 1161 GrowableArray<MirMethodLoweringInfo> method_lowering_infos_; 1162 static const uint64_t oat_data_flow_attributes_[kMirOpLast]; 1163 1164 friend class ClassInitCheckEliminationTest; 1165 friend class LocalValueNumberingTest; 1166}; 1167 1168} // namespace art 1169 1170#endif // ART_COMPILER_DEX_MIR_GRAPH_H_ 1171