mir_graph.h revision d4750f202170a448119c1813a964574bfea0dded
1/* 2 * Copyright (C) 2013 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_MIR_GRAPH_H_ 18#define ART_COMPILER_DEX_MIR_GRAPH_H_ 19 20#include <stdint.h> 21 22#include "dex_file.h" 23#include "dex_instruction.h" 24#include "compiler_ir.h" 25#include "invoke_type.h" 26#include "mir_field_info.h" 27#include "mir_method_info.h" 28#include "utils/arena_bit_vector.h" 29#include "utils/growable_array.h" 30#include "reg_storage.h" 31 32namespace art { 33 34enum InstructionAnalysisAttributePos { 35 kUninterestingOp = 0, 36 kArithmeticOp, 37 kFPOp, 38 kSingleOp, 39 kDoubleOp, 40 kIntOp, 41 kLongOp, 42 kBranchOp, 43 kInvokeOp, 44 kArrayOp, 45 kHeavyweightOp, 46 kSimpleConstOp, 47 kMoveOp, 48 kSwitch 49}; 50 51#define AN_NONE (1 << kUninterestingOp) 52#define AN_MATH (1 << kArithmeticOp) 53#define AN_FP (1 << kFPOp) 54#define AN_LONG (1 << kLongOp) 55#define AN_INT (1 << kIntOp) 56#define AN_SINGLE (1 << kSingleOp) 57#define AN_DOUBLE (1 << kDoubleOp) 58#define AN_FLOATMATH (1 << kFPOp) 59#define AN_BRANCH (1 << kBranchOp) 60#define AN_INVOKE (1 << kInvokeOp) 61#define AN_ARRAYOP (1 << kArrayOp) 62#define AN_HEAVYWEIGHT (1 << kHeavyweightOp) 63#define AN_SIMPLECONST (1 << kSimpleConstOp) 64#define AN_MOVE (1 << kMoveOp) 65#define AN_SWITCH (1 << kSwitch) 66#define AN_COMPUTATIONAL (AN_MATH | AN_ARRAYOP | AN_MOVE | AN_SIMPLECONST) 67 68enum DataFlowAttributePos { 69 kUA = 0, 70 kUB, 71 kUC, 72 kAWide, 73 kBWide, 74 kCWide, 75 kDA, 76 kIsMove, 77 kSetsConst, 78 kFormat35c, 79 kFormat3rc, 80 kNullCheckSrc0, // Null check of uses[0]. 81 kNullCheckSrc1, // Null check of uses[1]. 82 kNullCheckSrc2, // Null check of uses[2]. 83 kNullCheckOut0, // Null check out outgoing arg0. 84 kDstNonNull, // May assume dst is non-null. 85 kRetNonNull, // May assume retval is non-null. 86 kNullTransferSrc0, // Object copy src[0] -> dst. 87 kNullTransferSrcN, // Phi null check state transfer. 88 kRangeCheckSrc1, // Range check of uses[1]. 89 kRangeCheckSrc2, // Range check of uses[2]. 90 kRangeCheckSrc3, // Range check of uses[3]. 91 kFPA, 92 kFPB, 93 kFPC, 94 kCoreA, 95 kCoreB, 96 kCoreC, 97 kRefA, 98 kRefB, 99 kRefC, 100 kUsesMethodStar, // Implicit use of Method*. 101 kUsesIField, // Accesses an instance field (IGET/IPUT). 102 kUsesSField, // Accesses a static field (SGET/SPUT). 103 kDoLVN, // Worth computing local value numbers. 104}; 105 106#define DF_NOP UINT64_C(0) 107#define DF_UA (UINT64_C(1) << kUA) 108#define DF_UB (UINT64_C(1) << kUB) 109#define DF_UC (UINT64_C(1) << kUC) 110#define DF_A_WIDE (UINT64_C(1) << kAWide) 111#define DF_B_WIDE (UINT64_C(1) << kBWide) 112#define DF_C_WIDE (UINT64_C(1) << kCWide) 113#define DF_DA (UINT64_C(1) << kDA) 114#define DF_IS_MOVE (UINT64_C(1) << kIsMove) 115#define DF_SETS_CONST (UINT64_C(1) << kSetsConst) 116#define DF_FORMAT_35C (UINT64_C(1) << kFormat35c) 117#define DF_FORMAT_3RC (UINT64_C(1) << kFormat3rc) 118#define DF_NULL_CHK_0 (UINT64_C(1) << kNullCheckSrc0) 119#define DF_NULL_CHK_1 (UINT64_C(1) << kNullCheckSrc1) 120#define DF_NULL_CHK_2 (UINT64_C(1) << kNullCheckSrc2) 121#define DF_NULL_CHK_OUT0 (UINT64_C(1) << kNullCheckOut0) 122#define DF_NON_NULL_DST (UINT64_C(1) << kDstNonNull) 123#define DF_NON_NULL_RET (UINT64_C(1) << kRetNonNull) 124#define DF_NULL_TRANSFER_0 (UINT64_C(1) << kNullTransferSrc0) 125#define DF_NULL_TRANSFER_N (UINT64_C(1) << kNullTransferSrcN) 126#define DF_RANGE_CHK_1 (UINT64_C(1) << kRangeCheckSrc1) 127#define DF_RANGE_CHK_2 (UINT64_C(1) << kRangeCheckSrc2) 128#define DF_RANGE_CHK_3 (UINT64_C(1) << kRangeCheckSrc3) 129#define DF_FP_A (UINT64_C(1) << kFPA) 130#define DF_FP_B (UINT64_C(1) << kFPB) 131#define DF_FP_C (UINT64_C(1) << kFPC) 132#define DF_CORE_A (UINT64_C(1) << kCoreA) 133#define DF_CORE_B (UINT64_C(1) << kCoreB) 134#define DF_CORE_C (UINT64_C(1) << kCoreC) 135#define DF_REF_A (UINT64_C(1) << kRefA) 136#define DF_REF_B (UINT64_C(1) << kRefB) 137#define DF_REF_C (UINT64_C(1) << kRefC) 138#define DF_UMS (UINT64_C(1) << kUsesMethodStar) 139#define DF_IFIELD (UINT64_C(1) << kUsesIField) 140#define DF_SFIELD (UINT64_C(1) << kUsesSField) 141#define DF_LVN (UINT64_C(1) << kDoLVN) 142 143#define DF_HAS_USES (DF_UA | DF_UB | DF_UC) 144 145#define DF_HAS_DEFS (DF_DA) 146 147#define DF_HAS_NULL_CHKS (DF_NULL_CHK_0 | \ 148 DF_NULL_CHK_1 | \ 149 DF_NULL_CHK_2 | \ 150 DF_NULL_CHK_OUT0) 151 152#define DF_HAS_RANGE_CHKS (DF_RANGE_CHK_1 | \ 153 DF_RANGE_CHK_2 | \ 154 DF_RANGE_CHK_3) 155 156#define DF_HAS_NR_CHKS (DF_HAS_NULL_CHKS | \ 157 DF_HAS_RANGE_CHKS) 158 159#define DF_A_IS_REG (DF_UA | DF_DA) 160#define DF_B_IS_REG (DF_UB) 161#define DF_C_IS_REG (DF_UC) 162#define DF_IS_GETTER_OR_SETTER (DF_IS_GETTER | DF_IS_SETTER) 163#define DF_USES_FP (DF_FP_A | DF_FP_B | DF_FP_C) 164#define DF_NULL_TRANSFER (DF_NULL_TRANSFER_0 | DF_NULL_TRANSFER_N) 165enum OatMethodAttributes { 166 kIsLeaf, // Method is leaf. 167 kHasLoop, // Method contains simple loop. 168}; 169 170#define METHOD_IS_LEAF (1 << kIsLeaf) 171#define METHOD_HAS_LOOP (1 << kHasLoop) 172 173// Minimum field size to contain Dalvik v_reg number. 174#define VREG_NUM_WIDTH 16 175 176#define INVALID_SREG (-1) 177#define INVALID_VREG (0xFFFFU) 178#define INVALID_OFFSET (0xDEADF00FU) 179 180#define MIR_IGNORE_NULL_CHECK (1 << kMIRIgnoreNullCheck) 181#define MIR_NULL_CHECK_ONLY (1 << kMIRNullCheckOnly) 182#define MIR_IGNORE_RANGE_CHECK (1 << kMIRIgnoreRangeCheck) 183#define MIR_RANGE_CHECK_ONLY (1 << kMIRRangeCheckOnly) 184#define MIR_IGNORE_CLINIT_CHECK (1 << kMIRIgnoreClInitCheck) 185#define MIR_INLINED (1 << kMIRInlined) 186#define MIR_INLINED_PRED (1 << kMIRInlinedPred) 187#define MIR_CALLEE (1 << kMIRCallee) 188#define MIR_IGNORE_SUSPEND_CHECK (1 << kMIRIgnoreSuspendCheck) 189#define MIR_DUP (1 << kMIRDup) 190 191#define BLOCK_NAME_LEN 80 192 193typedef uint16_t BasicBlockId; 194static const BasicBlockId NullBasicBlockId = 0; 195 196/* 197 * In general, vreg/sreg describe Dalvik registers that originated with dx. However, 198 * it is useful to have compiler-generated temporary registers and have them treated 199 * in the same manner as dx-generated virtual registers. This struct records the SSA 200 * name of compiler-introduced temporaries. 201 */ 202struct CompilerTemp { 203 int32_t v_reg; // Virtual register number for temporary. 204 int32_t s_reg_low; // SSA name for low Dalvik word. 205}; 206 207enum CompilerTempType { 208 kCompilerTempVR, // A virtual register temporary. 209 kCompilerTempSpecialMethodPtr, // Temporary that keeps track of current method pointer. 210}; 211 212// When debug option enabled, records effectiveness of null and range check elimination. 213struct Checkstats { 214 int32_t null_checks; 215 int32_t null_checks_eliminated; 216 int32_t range_checks; 217 int32_t range_checks_eliminated; 218}; 219 220// Dataflow attributes of a basic block. 221struct BasicBlockDataFlow { 222 ArenaBitVector* use_v; 223 ArenaBitVector* def_v; 224 ArenaBitVector* live_in_v; 225 ArenaBitVector* phi_v; 226 int32_t* vreg_to_ssa_map; 227 ArenaBitVector* ending_check_v; // For null check and class init check elimination. 228}; 229 230/* 231 * Normalized use/def for a MIR operation using SSA names rather than vregs. Note that 232 * uses/defs retain the Dalvik convention that long operations operate on a pair of 32-bit 233 * vregs. For example, "ADD_LONG v0, v2, v3" would have 2 defs (v0/v1) and 4 uses (v2/v3, v4/v5). 234 * Following SSA renaming, this is the primary struct used by code generators to locate 235 * operand and result registers. This is a somewhat confusing and unhelpful convention that 236 * we may want to revisit in the future. 237 */ 238struct SSARepresentation { 239 int16_t num_uses; 240 int16_t num_defs; 241 int32_t* uses; 242 bool* fp_use; 243 int32_t* defs; 244 bool* fp_def; 245}; 246 247/* 248 * The Midlevel Intermediate Representation node, which may be largely considered a 249 * wrapper around a Dalvik byte code. 250 */ 251struct MIR { 252 /* 253 * TODO: remove embedded DecodedInstruction to save space, keeping only opcode. Recover 254 * additional fields on as-needed basis. Question: how to support MIR Pseudo-ops; probably 255 * need to carry aux data pointer. 256 */ 257 DecodedInstruction dalvikInsn; 258 uint16_t width; // Note: width can include switch table or fill array data. 259 NarrowDexOffset offset; // Offset of the instruction in code units. 260 uint16_t optimization_flags; 261 int16_t m_unit_index; // From which method was this MIR included 262 MIR* next; 263 SSARepresentation* ssa_rep; 264 union { 265 // Incoming edges for phi node. 266 BasicBlockId* phi_incoming; 267 // Establish link from check instruction (kMirOpCheck) to the actual throwing instruction. 268 MIR* throw_insn; 269 // Branch condition for fused cmp or select. 270 ConditionCode ccode; 271 // IGET/IPUT lowering info index, points to MIRGraph::ifield_lowering_infos_. Due to limit on 272 // the number of code points (64K) and size of IGET/IPUT insn (2), this will never exceed 32K. 273 uint32_t ifield_lowering_info; 274 // SGET/SPUT lowering info index, points to MIRGraph::sfield_lowering_infos_. Due to limit on 275 // the number of code points (64K) and size of SGET/SPUT insn (2), this will never exceed 32K. 276 uint32_t sfield_lowering_info; 277 // INVOKE data index, points to MIRGraph::method_lowering_infos_. 278 uint32_t method_lowering_info; 279 } meta; 280}; 281 282struct SuccessorBlockInfo; 283 284struct BasicBlock { 285 BasicBlockId id; 286 BasicBlockId dfs_id; 287 NarrowDexOffset start_offset; // Offset in code units. 288 BasicBlockId fall_through; 289 BasicBlockId taken; 290 BasicBlockId i_dom; // Immediate dominator. 291 uint16_t nesting_depth; 292 BBType block_type:4; 293 BlockListType successor_block_list_type:4; 294 bool visited:1; 295 bool hidden:1; 296 bool catch_entry:1; 297 bool explicit_throw:1; 298 bool conditional_branch:1; 299 bool terminated_by_return:1; // Block ends with a Dalvik return opcode. 300 bool dominates_return:1; // Is a member of return extended basic block. 301 bool use_lvn:1; // Run local value numbering on this block. 302 MIR* first_mir_insn; 303 MIR* last_mir_insn; 304 BasicBlockDataFlow* data_flow_info; 305 ArenaBitVector* dominators; 306 ArenaBitVector* i_dominated; // Set nodes being immediately dominated. 307 ArenaBitVector* dom_frontier; // Dominance frontier. 308 GrowableArray<BasicBlockId>* predecessors; 309 GrowableArray<SuccessorBlockInfo*>* successor_blocks; 310 311 void AppendMIR(MIR* mir); 312 void PrependMIR(MIR* mir); 313 void InsertMIRAfter(MIR* current_mir, MIR* new_mir); 314 315 /** 316 * @brief Used to obtain the next MIR that follows unconditionally. 317 * @details The implementation does not guarantee that a MIR does not 318 * follow even if this method returns nullptr. 319 * @param mir_graph the MIRGraph. 320 * @param current The MIR for which to find an unconditional follower. 321 * @return Returns the following MIR if one can be found. 322 */ 323 MIR* GetNextUnconditionalMir(MIRGraph* mir_graph, MIR* current); 324}; 325 326/* 327 * The "blocks" field in "successor_block_list" points to an array of elements with the type 328 * "SuccessorBlockInfo". For catch blocks, key is type index for the exception. For swtich 329 * blocks, key is the case value. 330 */ 331struct SuccessorBlockInfo { 332 BasicBlockId block; 333 int key; 334}; 335 336/* 337 * Whereas a SSA name describes a definition of a Dalvik vreg, the RegLocation describes 338 * the type of an SSA name (and, can also be used by code generators to record where the 339 * value is located (i.e. - physical register, frame, spill, etc.). For each SSA name (SReg) 340 * there is a RegLocation. 341 * A note on SSA names: 342 * o SSA names for Dalvik vRegs v0..vN will be assigned 0..N. These represent the "vN_0" 343 * names. Negative SSA names represent special values not present in the Dalvik byte code. 344 * For example, SSA name -1 represents an invalid SSA name, and SSA name -2 represents the 345 * the Method pointer. SSA names < -2 are reserved for future use. 346 * o The vN_0 names for non-argument Dalvik should in practice never be used (as they would 347 * represent the read of an undefined local variable). The first definition of the 348 * underlying Dalvik vReg will result in a vN_1 name. 349 * 350 * FIXME: The orig_sreg field was added as a workaround for llvm bitcode generation. With 351 * the latest restructuring, we should be able to remove it and rely on s_reg_low throughout. 352 */ 353struct RegLocation { 354 RegLocationType location:3; 355 unsigned wide:1; 356 unsigned defined:1; // Do we know the type? 357 unsigned is_const:1; // Constant, value in mir_graph->constant_values[]. 358 unsigned fp:1; // Floating point? 359 unsigned core:1; // Non-floating point? 360 unsigned ref:1; // Something GC cares about. 361 unsigned high_word:1; // High word of pair? 362 unsigned home:1; // Does this represent the home location? 363 VectorLengthType vec_len:3; // TODO: remove. Is this value in a vector register, and how big is it? 364 RegStorage reg; // Encoded physical registers. 365 int16_t s_reg_low; // SSA name for low Dalvik word. 366 int16_t orig_sreg; // TODO: remove after Bitcode gen complete 367 // and consolidate usage w/ s_reg_low. 368 369 bool IsVectorScalar() const { return vec_len == kVectorLength4 || vec_len == kVectorLength8;} 370}; 371 372/* 373 * Collection of information describing an invoke, and the destination of 374 * the subsequent MOVE_RESULT (if applicable). Collected as a unit to enable 375 * more efficient invoke code generation. 376 */ 377struct CallInfo { 378 int num_arg_words; // Note: word count, not arg count. 379 RegLocation* args; // One for each word of arguments. 380 RegLocation result; // Eventual target of MOVE_RESULT. 381 int opt_flags; 382 InvokeType type; 383 uint32_t dex_idx; 384 uint32_t index; // Method idx for invokes, type idx for FilledNewArray. 385 uintptr_t direct_code; 386 uintptr_t direct_method; 387 RegLocation target; // Target of following move_result. 388 bool skip_this; 389 bool is_range; 390 DexOffset offset; // Offset in code units. 391 MIR* mir; 392}; 393 394 395const RegLocation bad_loc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0, 0, kVectorNotUsed, 396 RegStorage(RegStorage::kInvalid), INVALID_SREG, INVALID_SREG}; 397 398class MIRGraph { 399 public: 400 MIRGraph(CompilationUnit* cu, ArenaAllocator* arena); 401 ~MIRGraph(); 402 403 /* 404 * Examine the graph to determine whether it's worthwile to spend the time compiling 405 * this method. 406 */ 407 bool SkipCompilation(); 408 409 /* 410 * Should we skip the compilation of this method based on its name? 411 */ 412 bool SkipCompilation(const std::string& methodname); 413 414 /* 415 * Parse dex method and add MIR at current insert point. Returns id (which is 416 * actually the index of the method in the m_units_ array). 417 */ 418 void InlineMethod(const DexFile::CodeItem* code_item, uint32_t access_flags, 419 InvokeType invoke_type, uint16_t class_def_idx, 420 uint32_t method_idx, jobject class_loader, const DexFile& dex_file); 421 422 /* Find existing block */ 423 BasicBlock* FindBlock(DexOffset code_offset) { 424 return FindBlock(code_offset, false, false, NULL); 425 } 426 427 const uint16_t* GetCurrentInsns() const { 428 return current_code_item_->insns_; 429 } 430 431 const uint16_t* GetInsns(int m_unit_index) const { 432 return m_units_[m_unit_index]->GetCodeItem()->insns_; 433 } 434 435 int GetNumBlocks() const { 436 return num_blocks_; 437 } 438 439 size_t GetNumDalvikInsns() const { 440 return cu_->code_item->insns_size_in_code_units_; 441 } 442 443 ArenaBitVector* GetTryBlockAddr() const { 444 return try_block_addr_; 445 } 446 447 BasicBlock* GetEntryBlock() const { 448 return entry_block_; 449 } 450 451 BasicBlock* GetExitBlock() const { 452 return exit_block_; 453 } 454 455 BasicBlock* GetBasicBlock(int block_id) const { 456 return (block_id == NullBasicBlockId) ? NULL : block_list_.Get(block_id); 457 } 458 459 size_t GetBasicBlockListCount() const { 460 return block_list_.Size(); 461 } 462 463 GrowableArray<BasicBlock*>* GetBlockList() { 464 return &block_list_; 465 } 466 467 GrowableArray<BasicBlockId>* GetDfsOrder() { 468 return dfs_order_; 469 } 470 471 GrowableArray<BasicBlockId>* GetDfsPostOrder() { 472 return dfs_post_order_; 473 } 474 475 GrowableArray<BasicBlockId>* GetDomPostOrder() { 476 return dom_post_order_traversal_; 477 } 478 479 int GetDefCount() const { 480 return def_count_; 481 } 482 483 ArenaAllocator* GetArena() { 484 return arena_; 485 } 486 487 void EnableOpcodeCounting() { 488 opcode_count_ = static_cast<int*>(arena_->Alloc(kNumPackedOpcodes * sizeof(int), 489 kArenaAllocMisc)); 490 } 491 492 void ShowOpcodeStats(); 493 494 DexCompilationUnit* GetCurrentDexCompilationUnit() const { 495 return m_units_[current_method_]; 496 } 497 498 /** 499 * @brief Dump a CFG into a dot file format. 500 * @param dir_prefix the directory the file will be created in. 501 * @param all_blocks does the dumper use all the basic blocks or use the reachable blocks. 502 * @param suffix does the filename require a suffix or not (default = nullptr). 503 */ 504 void DumpCFG(const char* dir_prefix, bool all_blocks, const char* suffix = nullptr); 505 506 bool HasFieldAccess() const { 507 return (merged_df_flags_ & (DF_IFIELD | DF_SFIELD)) != 0u; 508 } 509 510 bool HasStaticFieldAccess() const { 511 return (merged_df_flags_ & DF_SFIELD) != 0u; 512 } 513 514 bool HasInvokes() const { 515 // NOTE: These formats include the rare filled-new-array/range. 516 return (merged_df_flags_ & (DF_FORMAT_35C | DF_FORMAT_3RC)) != 0u; 517 } 518 519 void DoCacheFieldLoweringInfo(); 520 521 const MirIFieldLoweringInfo& GetIFieldLoweringInfo(MIR* mir) const { 522 DCHECK_LT(mir->meta.ifield_lowering_info, ifield_lowering_infos_.Size()); 523 return ifield_lowering_infos_.GetRawStorage()[mir->meta.ifield_lowering_info]; 524 } 525 526 const MirSFieldLoweringInfo& GetSFieldLoweringInfo(MIR* mir) const { 527 DCHECK_LT(mir->meta.sfield_lowering_info, sfield_lowering_infos_.Size()); 528 return sfield_lowering_infos_.GetRawStorage()[mir->meta.sfield_lowering_info]; 529 } 530 531 void DoCacheMethodLoweringInfo(); 532 533 const MirMethodLoweringInfo& GetMethodLoweringInfo(MIR* mir) { 534 DCHECK_LT(mir->meta.method_lowering_info, method_lowering_infos_.Size()); 535 return method_lowering_infos_.GetRawStorage()[mir->meta.method_lowering_info]; 536 } 537 538 void ComputeInlineIFieldLoweringInfo(uint16_t field_idx, MIR* invoke, MIR* iget_or_iput); 539 540 void InitRegLocations(); 541 542 void RemapRegLocations(); 543 544 void DumpRegLocTable(RegLocation* table, int count); 545 546 void BasicBlockOptimization(); 547 548 bool IsConst(int32_t s_reg) const { 549 return is_constant_v_->IsBitSet(s_reg); 550 } 551 552 bool IsConst(RegLocation loc) const { 553 return loc.orig_sreg < 0 ? false : IsConst(loc.orig_sreg); 554 } 555 556 int32_t ConstantValue(RegLocation loc) const { 557 DCHECK(IsConst(loc)); 558 return constant_values_[loc.orig_sreg]; 559 } 560 561 int32_t ConstantValue(int32_t s_reg) const { 562 DCHECK(IsConst(s_reg)); 563 return constant_values_[s_reg]; 564 } 565 566 int64_t ConstantValueWide(RegLocation loc) const { 567 DCHECK(IsConst(loc)); 568 return (static_cast<int64_t>(constant_values_[loc.orig_sreg + 1]) << 32) | 569 Low32Bits(static_cast<int64_t>(constant_values_[loc.orig_sreg])); 570 } 571 572 bool IsConstantNullRef(RegLocation loc) const { 573 return loc.ref && loc.is_const && (ConstantValue(loc) == 0); 574 } 575 576 int GetNumSSARegs() const { 577 return num_ssa_regs_; 578 } 579 580 void SetNumSSARegs(int new_num) { 581 /* 582 * TODO: It's theoretically possible to exceed 32767, though any cases which did 583 * would be filtered out with current settings. When orig_sreg field is removed 584 * from RegLocation, expand s_reg_low to handle all possible cases and remove DCHECK(). 585 */ 586 DCHECK_EQ(new_num, static_cast<int16_t>(new_num)); 587 num_ssa_regs_ = new_num; 588 } 589 590 unsigned int GetNumReachableBlocks() const { 591 return num_reachable_blocks_; 592 } 593 594 int GetUseCount(int vreg) const { 595 return use_counts_.Get(vreg); 596 } 597 598 int GetRawUseCount(int vreg) const { 599 return raw_use_counts_.Get(vreg); 600 } 601 602 int GetSSASubscript(int ssa_reg) const { 603 return ssa_subscripts_->Get(ssa_reg); 604 } 605 606 RegLocation GetRawSrc(MIR* mir, int num) { 607 DCHECK(num < mir->ssa_rep->num_uses); 608 RegLocation res = reg_location_[mir->ssa_rep->uses[num]]; 609 return res; 610 } 611 612 RegLocation GetRawDest(MIR* mir) { 613 DCHECK_GT(mir->ssa_rep->num_defs, 0); 614 RegLocation res = reg_location_[mir->ssa_rep->defs[0]]; 615 return res; 616 } 617 618 RegLocation GetDest(MIR* mir) { 619 RegLocation res = GetRawDest(mir); 620 DCHECK(!res.wide); 621 return res; 622 } 623 624 RegLocation GetSrc(MIR* mir, int num) { 625 RegLocation res = GetRawSrc(mir, num); 626 DCHECK(!res.wide); 627 return res; 628 } 629 630 RegLocation GetDestWide(MIR* mir) { 631 RegLocation res = GetRawDest(mir); 632 DCHECK(res.wide); 633 return res; 634 } 635 636 RegLocation GetSrcWide(MIR* mir, int low) { 637 RegLocation res = GetRawSrc(mir, low); 638 DCHECK(res.wide); 639 return res; 640 } 641 642 RegLocation GetBadLoc() { 643 return bad_loc; 644 } 645 646 int GetMethodSReg() const { 647 return method_sreg_; 648 } 649 650 /** 651 * @brief Used to obtain the number of compiler temporaries being used. 652 * @return Returns the number of compiler temporaries. 653 */ 654 size_t GetNumUsedCompilerTemps() const { 655 size_t total_num_temps = compiler_temps_.Size(); 656 DCHECK_LE(num_non_special_compiler_temps_, total_num_temps); 657 return total_num_temps; 658 } 659 660 /** 661 * @brief Used to obtain the number of non-special compiler temporaries being used. 662 * @return Returns the number of non-special compiler temporaries. 663 */ 664 size_t GetNumNonSpecialCompilerTemps() const { 665 return num_non_special_compiler_temps_; 666 } 667 668 /** 669 * @brief Used to set the total number of available non-special compiler temporaries. 670 * @details Can fail setting the new max if there are more temps being used than the new_max. 671 * @param new_max The new maximum number of non-special compiler temporaries. 672 * @return Returns true if the max was set and false if failed to set. 673 */ 674 bool SetMaxAvailableNonSpecialCompilerTemps(size_t new_max) { 675 if (new_max < GetNumNonSpecialCompilerTemps()) { 676 return false; 677 } else { 678 max_available_non_special_compiler_temps_ = new_max; 679 return true; 680 } 681 } 682 683 /** 684 * @brief Provides the number of non-special compiler temps available. 685 * @details Even if this returns zero, special compiler temps are guaranteed to be available. 686 * @return Returns the number of available temps. 687 */ 688 size_t GetNumAvailableNonSpecialCompilerTemps(); 689 690 /** 691 * @brief Used to obtain an existing compiler temporary. 692 * @param index The index of the temporary which must be strictly less than the 693 * number of temporaries. 694 * @return Returns the temporary that was asked for. 695 */ 696 CompilerTemp* GetCompilerTemp(size_t index) const { 697 return compiler_temps_.Get(index); 698 } 699 700 /** 701 * @brief Used to obtain the maximum number of compiler temporaries that can be requested. 702 * @return Returns the maximum number of compiler temporaries, whether used or not. 703 */ 704 size_t GetMaxPossibleCompilerTemps() const { 705 return max_available_special_compiler_temps_ + max_available_non_special_compiler_temps_; 706 } 707 708 /** 709 * @brief Used to obtain a new unique compiler temporary. 710 * @param ct_type Type of compiler temporary requested. 711 * @param wide Whether we should allocate a wide temporary. 712 * @return Returns the newly created compiler temporary. 713 */ 714 CompilerTemp* GetNewCompilerTemp(CompilerTempType ct_type, bool wide); 715 716 bool MethodIsLeaf() { 717 return attributes_ & METHOD_IS_LEAF; 718 } 719 720 RegLocation GetRegLocation(int index) { 721 DCHECK((index >= 0) && (index < num_ssa_regs_)); 722 return reg_location_[index]; 723 } 724 725 RegLocation GetMethodLoc() { 726 return reg_location_[method_sreg_]; 727 } 728 729 bool IsBackedge(BasicBlock* branch_bb, BasicBlockId target_bb_id) { 730 return ((target_bb_id != NullBasicBlockId) && 731 (GetBasicBlock(target_bb_id)->start_offset <= branch_bb->start_offset)); 732 } 733 734 bool IsBackwardsBranch(BasicBlock* branch_bb) { 735 return IsBackedge(branch_bb, branch_bb->taken) || IsBackedge(branch_bb, branch_bb->fall_through); 736 } 737 738 void CountBranch(DexOffset target_offset) { 739 if (target_offset <= current_offset_) { 740 backward_branches_++; 741 } else { 742 forward_branches_++; 743 } 744 } 745 746 int GetBranchCount() { 747 return backward_branches_ + forward_branches_; 748 } 749 750 bool IsPseudoMirOp(Instruction::Code opcode) { 751 return static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst); 752 } 753 754 bool IsPseudoMirOp(int opcode) { 755 return opcode >= static_cast<int>(kMirOpFirst); 756 } 757 758 // Is this vreg in the in set? 759 bool IsInVReg(int vreg) { 760 return (vreg >= cu_->num_regs); 761 } 762 763 void DumpCheckStats(); 764 MIR* FindMoveResult(BasicBlock* bb, MIR* mir); 765 int SRegToVReg(int ssa_reg) const; 766 void VerifyDataflow(); 767 void CheckForDominanceFrontier(BasicBlock* dom_bb, const BasicBlock* succ_bb); 768 void EliminateNullChecksAndInferTypesStart(); 769 bool EliminateNullChecksAndInferTypes(BasicBlock *bb); 770 void EliminateNullChecksAndInferTypesEnd(); 771 bool EliminateClassInitChecksGate(); 772 bool EliminateClassInitChecks(BasicBlock* bb); 773 void EliminateClassInitChecksEnd(); 774 /* 775 * Type inference handling helpers. Because Dalvik's bytecode is not fully typed, 776 * we have to do some work to figure out the sreg type. For some operations it is 777 * clear based on the opcode (i.e. ADD_FLOAT v0, v1, v2), but for others (MOVE), we 778 * may never know the "real" type. 779 * 780 * We perform the type inference operation by using an iterative walk over 781 * the graph, propagating types "defined" by typed opcodes to uses and defs in 782 * non-typed opcodes (such as MOVE). The Setxx(index) helpers are used to set defined 783 * types on typed opcodes (such as ADD_INT). The Setxx(index, is_xx) form is used to 784 * propagate types through non-typed opcodes such as PHI and MOVE. The is_xx flag 785 * tells whether our guess of the type is based on a previously typed definition. 786 * If so, the defined type takes precedence. Note that it's possible to have the same sreg 787 * show multiple defined types because dx treats constants as untyped bit patterns. 788 * The return value of the Setxx() helpers says whether or not the Setxx() action changed 789 * the current guess, and is used to know when to terminate the iterative walk. 790 */ 791 bool SetFp(int index, bool is_fp); 792 bool SetFp(int index); 793 bool SetCore(int index, bool is_core); 794 bool SetCore(int index); 795 bool SetRef(int index, bool is_ref); 796 bool SetRef(int index); 797 bool SetWide(int index, bool is_wide); 798 bool SetWide(int index); 799 bool SetHigh(int index, bool is_high); 800 bool SetHigh(int index); 801 802 char* GetDalvikDisassembly(const MIR* mir); 803 void ReplaceSpecialChars(std::string& str); 804 std::string GetSSAName(int ssa_reg); 805 std::string GetSSANameWithConst(int ssa_reg, bool singles_only); 806 void GetBlockName(BasicBlock* bb, char* name); 807 const char* GetShortyFromTargetIdx(int); 808 void DumpMIRGraph(); 809 CallInfo* NewMemCallInfo(BasicBlock* bb, MIR* mir, InvokeType type, bool is_range); 810 BasicBlock* NewMemBB(BBType block_type, int block_id); 811 MIR* AdvanceMIR(BasicBlock** p_bb, MIR* mir); 812 BasicBlock* NextDominatedBlock(BasicBlock* bb); 813 bool LayoutBlocks(BasicBlock* bb); 814 815 bool InlineCallsGate(); 816 void InlineCallsStart(); 817 void InlineCalls(BasicBlock* bb); 818 void InlineCallsEnd(); 819 820 /** 821 * @brief Perform the initial preparation for the Method Uses. 822 */ 823 void InitializeMethodUses(); 824 825 /** 826 * @brief Perform the initial preparation for the Constant Propagation. 827 */ 828 void InitializeConstantPropagation(); 829 830 /** 831 * @brief Perform the initial preparation for the SSA Transformation. 832 */ 833 void InitializeSSATransformation(); 834 835 /** 836 * @brief Insert a the operands for the Phi nodes. 837 * @param bb the considered BasicBlock. 838 * @return true 839 */ 840 bool InsertPhiNodeOperands(BasicBlock* bb); 841 842 /** 843 * @brief Perform constant propagation on a BasicBlock. 844 * @param bb the considered BasicBlock. 845 */ 846 void DoConstantPropagation(BasicBlock* bb); 847 848 /** 849 * @brief Count the uses in the BasicBlock 850 * @param bb the BasicBlock 851 */ 852 void CountUses(struct BasicBlock* bb); 853 854 /** 855 * @brief Combine BasicBlocks 856 * @param the BasicBlock we are considering 857 */ 858 void CombineBlocks(BasicBlock* bb); 859 860 void ClearAllVisitedFlags(); 861 /* 862 * IsDebugBuild sanity check: keep track of the Dex PCs for catch entries so that later on 863 * we can verify that all catch entries have native PC entries. 864 */ 865 std::set<uint32_t> catches_; 866 867 // TODO: make these private. 868 RegLocation* reg_location_; // Map SSA names to location. 869 SafeMap<unsigned int, unsigned int> block_id_map_; // Block collapse lookup cache. 870 871 static const uint64_t oat_data_flow_attributes_[kMirOpLast]; 872 static const char* extended_mir_op_names_[kMirOpLast - kMirOpFirst]; 873 static const uint32_t analysis_attributes_[kMirOpLast]; 874 875 private: 876 int FindCommonParent(int block1, int block2); 877 void ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1, 878 const ArenaBitVector* src2); 879 void HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v, 880 ArenaBitVector* live_in_v, int dalvik_reg_id); 881 void HandleDef(ArenaBitVector* def_v, int dalvik_reg_id); 882 void CompilerInitializeSSAConversion(); 883 bool DoSSAConversion(BasicBlock* bb); 884 bool InvokeUsesMethodStar(MIR* mir); 885 int ParseInsn(const uint16_t* code_ptr, DecodedInstruction* decoded_instruction); 886 bool ContentIsInsn(const uint16_t* code_ptr); 887 BasicBlock* SplitBlock(DexOffset code_offset, BasicBlock* orig_block, 888 BasicBlock** immed_pred_block_p); 889 BasicBlock* FindBlock(DexOffset code_offset, bool split, bool create, 890 BasicBlock** immed_pred_block_p); 891 void ProcessTryCatchBlocks(); 892 BasicBlock* ProcessCanBranch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 893 int flags, const uint16_t* code_ptr, const uint16_t* code_end); 894 BasicBlock* ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 895 int flags); 896 BasicBlock* ProcessCanThrow(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 897 int flags, ArenaBitVector* try_block_addr, const uint16_t* code_ptr, 898 const uint16_t* code_end); 899 int AddNewSReg(int v_reg); 900 void HandleSSAUse(int* uses, int dalvik_reg, int reg_index); 901 void HandleSSADef(int* defs, int dalvik_reg, int reg_index); 902 void DataFlowSSAFormat35C(MIR* mir); 903 void DataFlowSSAFormat3RC(MIR* mir); 904 bool FindLocalLiveIn(BasicBlock* bb); 905 bool InferTypeAndSize(BasicBlock* bb, MIR* mir, bool changed); 906 bool VerifyPredInfo(BasicBlock* bb); 907 BasicBlock* NeedsVisit(BasicBlock* bb); 908 BasicBlock* NextUnvisitedSuccessor(BasicBlock* bb); 909 void MarkPreOrder(BasicBlock* bb); 910 void RecordDFSOrders(BasicBlock* bb); 911 void ComputeDFSOrders(); 912 void ComputeDefBlockMatrix(); 913 void ComputeDomPostOrderTraversal(BasicBlock* bb); 914 void ComputeDominators(); 915 void InsertPhiNodes(); 916 void DoDFSPreOrderSSARename(BasicBlock* block); 917 void SetConstant(int32_t ssa_reg, int value); 918 void SetConstantWide(int ssa_reg, int64_t value); 919 int GetSSAUseCount(int s_reg); 920 bool BasicBlockOpt(BasicBlock* bb); 921 bool BuildExtendedBBList(struct BasicBlock* bb); 922 bool FillDefBlockMatrix(BasicBlock* bb); 923 void InitializeDominationInfo(BasicBlock* bb); 924 bool ComputeblockIDom(BasicBlock* bb); 925 bool ComputeBlockDominators(BasicBlock* bb); 926 bool SetDominators(BasicBlock* bb); 927 bool ComputeBlockLiveIns(BasicBlock* bb); 928 bool ComputeDominanceFrontier(BasicBlock* bb); 929 930 void CountChecks(BasicBlock* bb); 931 void AnalyzeBlock(BasicBlock* bb, struct MethodStats* stats); 932 bool ComputeSkipCompilation(struct MethodStats* stats, bool skip_default); 933 934 CompilationUnit* const cu_; 935 GrowableArray<int>* ssa_base_vregs_; 936 GrowableArray<int>* ssa_subscripts_; 937 // Map original Dalvik virtual reg i to the current SSA name. 938 int* vreg_to_ssa_map_; // length == method->registers_size 939 int* ssa_last_defs_; // length == method->registers_size 940 ArenaBitVector* is_constant_v_; // length == num_ssa_reg 941 int* constant_values_; // length == num_ssa_reg 942 // Use counts of ssa names. 943 GrowableArray<uint32_t> use_counts_; // Weighted by nesting depth 944 GrowableArray<uint32_t> raw_use_counts_; // Not weighted 945 unsigned int num_reachable_blocks_; 946 GrowableArray<BasicBlockId>* dfs_order_; 947 GrowableArray<BasicBlockId>* dfs_post_order_; 948 GrowableArray<BasicBlockId>* dom_post_order_traversal_; 949 int* i_dom_list_; 950 ArenaBitVector** def_block_matrix_; // num_dalvik_register x num_blocks. 951 ArenaBitVector* temp_dalvik_register_v_; 952 UniquePtr<ScopedArenaAllocator> temp_scoped_alloc_; 953 uint16_t* temp_insn_data_; 954 uint32_t temp_bit_vector_size_; 955 ArenaBitVector* temp_bit_vector_; 956 static const int kInvalidEntry = -1; 957 GrowableArray<BasicBlock*> block_list_; 958 ArenaBitVector* try_block_addr_; 959 BasicBlock* entry_block_; 960 BasicBlock* exit_block_; 961 int num_blocks_; 962 const DexFile::CodeItem* current_code_item_; 963 GrowableArray<uint16_t> dex_pc_to_block_map_; // FindBlock lookup cache. 964 std::vector<DexCompilationUnit*> m_units_; // List of methods included in this graph 965 typedef std::pair<int, int> MIRLocation; // Insert point, (m_unit_ index, offset) 966 std::vector<MIRLocation> method_stack_; // Include stack 967 int current_method_; 968 DexOffset current_offset_; // Offset in code units 969 int def_count_; // Used to estimate size of ssa name storage. 970 int* opcode_count_; // Dex opcode coverage stats. 971 int num_ssa_regs_; // Number of names following SSA transformation. 972 std::vector<BasicBlockId> extended_basic_blocks_; // Heads of block "traces". 973 int method_sreg_; 974 unsigned int attributes_; 975 Checkstats* checkstats_; 976 ArenaAllocator* arena_; 977 int backward_branches_; 978 int forward_branches_; 979 GrowableArray<CompilerTemp*> compiler_temps_; 980 size_t num_non_special_compiler_temps_; 981 size_t max_available_non_special_compiler_temps_; 982 size_t max_available_special_compiler_temps_; 983 bool punt_to_interpreter_; // Difficult or not worthwhile - just interpret. 984 uint64_t merged_df_flags_; 985 GrowableArray<MirIFieldLoweringInfo> ifield_lowering_infos_; 986 GrowableArray<MirSFieldLoweringInfo> sfield_lowering_infos_; 987 GrowableArray<MirMethodLoweringInfo> method_lowering_infos_; 988 989 friend class ClassInitCheckEliminationTest; 990 friend class LocalValueNumberingTest; 991}; 992 993} // namespace art 994 995#endif // ART_COMPILER_DEX_MIR_GRAPH_H_ 996